Renesas SH7709S Manual Do Utilizador
Rev. 5.00, 09/03, page 129 of 760
Interrupt Source
INTEVT Code
(INTEVT2 Code)
(INTEVT2 Code)
Interrupt
Priority
(Initial Value)
Priority
(Initial Value)
IPR (Bit
Numbers)
Numbers)
Priority
within IPR
Setting Unit
within IPR
Setting Unit
Default
Priority
Priority
SCIF
ERI2
H'200–3C0
*
1
(H'900) 0–15 (0)
IPRE (7–4)
High
High
RXI2
H'200–3C0
*
1
(H'920)
BRI2
H'200–3C0
*
1
(H'940)
TXI2
H'200–3C0
*
1
(H'960)
Low
ADC
ADI
H'200–3C0
*
1
(H'980) 0–15 (0)
IPRE (3–0)
—
TMU0 TUNI0
H'400 (H'400)
0–15 (0)
IPRA (15–12) —
TMU1 TUNI1
H'420 (H'420)
0–15 (0)
IPRA (11–8)
—
TMU2 TUNI2
H'440 (H'440)
0–15 (0)
IPRA (7–4)
High
TICPI2
H'460 (H'460)
Low
RTC
ATI
H'480 (H'480)
0–15 (0)
IPRA (3–0)
High
PRI
H'4A0 (H'4A0)
CUI
H'4C0 (H'4C0)
Low
SCI
ERI
H'4E0 (H'4E0)
0–15 (0)
IPRB (7–4)
High
RXI
H'500 (H'500)
TXI
H'520 (H'520)
TEI
H'540 (H'540)
Low
WDT
ITI
H'560 (H'560)
0–15 (0)
IPRB (15–12) —
REF
RCMI
H'580 (H'580)
0–15 (0)
IPRB (11–8)
High
ROVI
H'5A0 (H'5A0)
Low
Low
Notes: 1. The code corresponding to an interrupt level shown in table 6.6 is set.
2. When
IRLS3
–
IRLS0
are enabled, IRL is the higher level of
IRL3
–
IRL0
and
IRLS3
–
IRLS0
.