Renesas SH7709S Manual Do Utilizador

Rev. 5.00, 09/03, page 176 of 760

4. Register specifications

BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BARB = H'0003722E,
BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000008, BASRA = H'80, BASRB = H'70

Specified conditions: Channel A/channel B sequence mode

•

Channel  A

Address:

H'00037226, Address mask: H'00000000, ASID: H'80

Bus cycle: CPU/instruction fetch (before instruction execution)/write/word

•

Channel  B

Address:

H'0003722E, Address mask: H'00000000, ASID: H'70

Data:

H'00000000, Data mask: H'00000000

Bus cycle: CPU/instruction fetch (before instruction execution)/read/word

Since instruction fetch is not a write cycle on channel A, a sequence condition does not match.
Therefore, no user break occurs.

5. Register specifications

BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BARB = H'00001000,
BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00300001, BETR = H'0005

Specified conditions: Channel A/channel B independent mode

•

Channel  A

Address: H'00000500, 

Address 

mask: 

H'00000000

Bus cycle:  CPU/instruction fetch (before instruction execution)/read/longword

•

Channel  B

Address:

H'00001000, Address mask: H'00000000

Data:

H'00000000, Data mask: H'00000000

Bus cycle: CPU/instruction fetch (before instruction execution)/read/longword

The number of execution-times break enable (5 times)

On channel A, a user break occurs before an instruction of address H'00000500 is executed.
On channel B, a user break occurs before the fifth instruction execution after instructions of
address H'00001000 are executed four times.