Renesas SH7709S Manual Do Utilizador
Rev. 5.00, 09/03, page xxxii of xliv
Figure 8.3
Manual Reset STATUS Output............................................................................ 193
Figure 8.4
Standby to Interrupt STATUS Output.................................................................. 194
Figure 8.5
Standby to Power-On Reset STATUS Output...................................................... 195
Figure 8.6
Standby to Manual Reset STATUS Output.......................................................... 196
Figure 8.7
Sleep to Interrupt STATUS Output ...................................................................... 196
Figure 8.8
Sleep to Power-On Reset STATUS Output.......................................................... 197
Figure 8.9
Sleep to Manual Reset STATUS Output .............................................................. 198
Figure 8.10
Hardware Standby Mode (When CA Goes Low in Normal Operation)............... 200
Figure 8.11
Hardware Standby Mode Timing (When CA Goes Low during WDT Operation
on Standby Mode Cancellation) ........................................................................... 201
on Standby Mode Cancellation) ........................................................................... 201
Figure 9.1
Block Diagram of Clock Pulse Generator ............................................................ 204
Figure 9.2
Block Diagram of WDT ....................................................................................... 214
Figure 9.3
Writing to WTCNT and WTCSR......................................................................... 217
Figure 9.4
Points for Attention when Using Crystal Resonator............................................. 220
Figure 9.5
Points for Attention when Using PLL Oscillator Circuit ..................................... 221
Figure 10.1
Block Diagram of Bus State Controller................................................................ 225
Figure 10.2
Correspondence between Logical Address Space and Physical Address Space .. 229
Figure 10.3
Physical Space Allocation .................................................................................... 231
Figure 10.4
PCMCIA Space Allocation .................................................................................. 232
Figure 10.5
Writing to RFCR, RTCSR, RTCNT, and RTCOR............................................... 257
Figure 10.6
Basic Timing of Basic Interface ........................................................................... 269
Figure 10.7
Example of 32-Bit Data-Width Static RAM Connection ..................................... 270
Figure 10.8
Example of 16-Bit Data-Width Static RAM Connection ..................................... 271
Figure 10.9
Example of 8-Bit Data-Width Static RAM Connection ....................................... 272
Figure 10.10 Basic Interface Wait Timing (Software Wait Only) ............................................. 273
Figure 10.11 Basic Interface Wait State Timing (Wait State Insertion by
Figure 10.11 Basic Interface Wait State Timing (Wait State Insertion by
WAIT Signal
WAITSEL = 1)..................................................................................................... 275
Figure 10.12 Example of 64-Mbit Synchronous DRAM Connection (32-Bit Bus Width)........ 277
Figure 10.13 Example of 64-Mbit Synchronous DRAM Connection (16-Bit Bus Width)........ 278
Figure 10.14 Basic Timing for Synchronous DRAM Burst Read ............................................. 282
Figure 10.15 Synchronous DRAM Burst Read Wait Specification Timing .............................. 283
Figure 10.16 Basic Timing for Synchronous DRAM Single Read............................................ 284
Figure 10.17 Basic Timing for Synchronous DRAM Burst Write ............................................ 286
Figure 10.18 Basic Timing for Synchronous DRAM Single Write........................................... 288
Figure 10.19 Burst Read Timing (No Precharge) ...................................................................... 291
Figure 10.20 Burst Read Timing (Same Row Address) ............................................................ 292
Figure 10.21 Burst Read Timing (Different Row Addresses) ................................................... 293
Figure 10.22 Burst Write Timing (No Precharge) ..................................................................... 294
Figure 10.23 Burst Write Timing (Same Row Address) ........................................................... 295
Figure 10.24 Burst Write Timing (Different Row Addresses) .................................................. 296
Figure 10.25 Auto-Refresh Operation ....................................................................................... 298
Figure 10.26 Synchronous DRAM Auto-Refresh Timing......................................................... 299
Figure 10.27 Synchronous DRAM Self-Refresh Timing .......................................................... 301
Figure 10.13 Example of 64-Mbit Synchronous DRAM Connection (16-Bit Bus Width)........ 278
Figure 10.14 Basic Timing for Synchronous DRAM Burst Read ............................................. 282
Figure 10.15 Synchronous DRAM Burst Read Wait Specification Timing .............................. 283
Figure 10.16 Basic Timing for Synchronous DRAM Single Read............................................ 284
Figure 10.17 Basic Timing for Synchronous DRAM Burst Write ............................................ 286
Figure 10.18 Basic Timing for Synchronous DRAM Single Write........................................... 288
Figure 10.19 Burst Read Timing (No Precharge) ...................................................................... 291
Figure 10.20 Burst Read Timing (Same Row Address) ............................................................ 292
Figure 10.21 Burst Read Timing (Different Row Addresses) ................................................... 293
Figure 10.22 Burst Write Timing (No Precharge) ..................................................................... 294
Figure 10.23 Burst Write Timing (Same Row Address) ........................................................... 295
Figure 10.24 Burst Write Timing (Different Row Addresses) .................................................. 296
Figure 10.25 Auto-Refresh Operation ....................................................................................... 298
Figure 10.26 Synchronous DRAM Auto-Refresh Timing......................................................... 299
Figure 10.27 Synchronous DRAM Self-Refresh Timing .......................................................... 301