Renesas SH7709S Manual Do Utilizador

Rev. 5.00, 09/03, page xxxiii of xliv

Figure 10.28 Synchronous DRAM Mode Write Timing ........................................................... 303
Figure 10.29 Burst ROM Wait Access Timing ......................................................................... 305
Figure 10.30 Burst ROM Basic Access Timing ........................................................................ 306
Figure 10.31 Example of PCMCIA Interface ............................................................................ 308
Figure 10.32 Basic Timing for PCMCIA Memory Card Interface ............................................ 310
Figure 10.33 Wait Timing for PCMCIA Memory Card Interface ............................................. 311
Figure 10.34 Basic Timing for PCMCIA Memory Card Interface Burst Access ...................... 312
Figure 10.35 Wait Timing for PCMCIA Memory Card Interface Burst Access ....................... 313
Figure 10.36 PCMCIA Space Allocation .................................................................................. 314
Figure 10.37 Basic Timing for PCMCIA I/O Card Interface .................................................... 316
Figure 10.38 Wait Timing for PCMCIA I/O Card Interface ..................................................... 317
Figure 10.39 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface ............................ 318
Figure 10.40 Waits between Access Cycles .............................................................................. 320
Figure 10.41 Pull-Up Timing for Pins A25 to A0 ..................................................................... 321
Figure 10.42 Pull-Up Timing for Pins D31 to D0 (Read Cycle) ............................................... 322
Figure 10.43 Pull-Up Timing for Pins D31 to D0 (Write Cycle) .............................................. 322
Figure 11.1

Block Diagram of DMAC .................................................................................... 329

Figure 11.2

DMAC Transfer Flowchart .................................................................................. 346

Figure 11.3

Round-Robin Mode.............................................................................................. 350

Figure 11.4

Changes in Channel Priority in Round-Robin Mode............................................ 351

Figure 11.5

Operation of Direct Address Mode in Dual Address Mode ................................. 353

Figure 11.6

Example of DMA Transfer Timing in the Direct Address Mode in Dual Mode
(Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory). 354

Figure 11.7

Indirect Address Operation in Dual Address Mode (When External Memory
Space has a 16-Bit Width) .................................................................................... 355

Figure 11.8

Example of Transfer Timing in the Indirect Address Mode in Dual Address
Mode .................................................................................................................... 356

Figure 11.9

Data Flow in Single Address Mode...................................................................... 357

Figure 11.10 Example of DMA Transfer Timing in Single Address Mode .............................. 358
Figure 11.11 Example of DMA Transfer Timing in Single Address Mode (16-byte Transfer,

External Memory Space (Ordinary Memory) 

→

 External Device with DACK) . 359

Figure 11.12 Example of DMA Transfer in Cycle-Steal Mode................................................. 360
Figure 11.13 Example of Transfer in Burst Mode ..................................................................... 360
Figure 11.14 Bus State when Multiple Channels Are Operating............................................... 362
Figure 11.15 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles) ..................................... 365
Figure 11.16 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles) ..................................... 366
Figure 11.17 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DMA RD Access:

4 Cycles)............................................................................................................... 367

Figure 11.18 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, 

DREQ Input Delayed). 368

Figure 11.19 Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles) ...................................... 369
Figure 11.20 Burst Mode, Level Input ...................................................................................... 370
Figure 11.21 Burst Mode, Edge Input ....................................................................................... 371
Figure 11.22 Source Address Reload Function Diagram........................................................... 372