Renesas SH7709S Manual Do Utilizador
Rev. 5.00, 09/03, page xxxvii of xliv
Figure 23.19 Burst ROM Bus Cycle (No Wait) ........................................................................ 678
Figure 23.20 Burst ROM Bus Cycle (Two Waits) .................................................................... 679
Figure 23.21 Burst ROM Bus Cycle (External Wait, WAITSEL = 1) ...................................... 680
Figure 23.22 Synchronous DRAM Read Bus Cycle (RCD
Figure 23.20 Burst ROM Bus Cycle (Two Waits) .................................................................... 679
Figure 23.21 Burst ROM Bus Cycle (External Wait, WAITSEL = 1) ...................................... 680
Figure 23.22 Synchronous DRAM Read Bus Cycle (RCD
=
0, CAS Latency
=
1, TPC
=
0) .. 681
Figure 23.23 Synchronous DRAM Read Bus Cycle (RCD
=
2, CAS Latency
=
2, TPC
=
1) .. 682
Figure 23.24 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read
×
4),
RCD
=
0, CAS Latency
=
1, TPC
=
1) ................................................................. 683
Figure 23.25 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read
×
4),
RCD
=
1, CAS Latency
=
3, TPC
=
0) ................................................................. 684
Figure 23.26 Synchronous DRAM Write Bus Cycle (RCD
=
0, TPC
=
0, TRWL = 0)............ 685
Figure 23.27 Synchronous DRAM Write Bus Cycle (RCD
=
2, TPC
=
1, TRWL = 1)............ 686
Figure 23.28 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write
×
4),
RCD
=
0, TPC
=
1, TRWL = 0) ........................................................................... 687
Figure 23.29 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write
×
4),
RCD
=
1, TPC
=
0, TRWL = 0) ........................................................................... 688
Figure 23.30 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row
Address, CAS Latency = 1).................................................................................. 689
Figure 23.31 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row
Address, CAS Latency = 2).................................................................................. 690
Figure 23.32 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Different Row
Address, TPC = 0, RCD = 0, CAS Latency = 1) .................................................. 691
Figure 23.33 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Different Row
Address, TPC = 1, RCD = 0, CAS Latency = 1) .................................................. 692
Figure 23.34 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Same Row
Address) ............................................................................................................... 693
Figure 23.35 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row
Address, TPC = 0, RCD = 0) ............................................................................... 694
Figure 23.36 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row
Address, TPC = 1, RCD = 1) ............................................................................... 695
Figure 23.37 Synchronous DRAM Auto-Refresh Timing (TRAS = 1, TPC = 1) ..................... 696
Figure 23.38 Synchronous DRAM Self-Refresh Cycle (TRAS
Figure 23.38 Synchronous DRAM Self-Refresh Cycle (TRAS
=
1, TPC
=
1) ......................... 697
Figure 23.39 Synchronous DRAM Mode Register Write Cycle ............................................... 698
Figure 23.40 PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait) ............................. 699
Figure 23.41 PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait,
Figure 23.40 PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait) ............................. 699
Figure 23.41 PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait,
WAITSEL = 1)..................................................................................................... 700
Figure 23.42 PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait).......... 701
Figure 23.43 PCMCIA Memory Bus Cycle (Burst Read, TED = 1, TEH = 1, Two Waits,
Figure 23.43 PCMCIA Memory Bus Cycle (Burst Read, TED = 1, TEH = 1, Two Waits,
Burst Pitch = 3, WAITSEL = 1) ........................................................................... 702
Figure 23.44 PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait)...................................... 703
Figure 23.45 PCMCIA I/O Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait,
Figure 23.45 PCMCIA I/O Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait,
WAITSEL = 1)..................................................................................................... 704
Figure 23.46 PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, One Wait, Bus Sizing,
WAITSEL = 1)..................................................................................................... 705