Renesas SH7709S Manual Do Utilizador
Rev. 5.00, 09/03, page xxxviii of xliv
Figure 23.47 TCLK Input Timing ............................................................................................. 707
Figure 23.48 TCLK Clock Input Timing................................................................................... 707
Figure 23.49 Oscillation Settling Time at RTC Crystal Oscillator Power-on............................ 707
Figure 23.50 SCK Input Clock Timing ..................................................................................... 707
Figure 23.51 SCI I/O Timing in Clock Synchronous Mode ...................................................... 708
Figure 23.52 I/O Port Timing .................................................................................................... 708
Figure 23.53
Figure 23.48 TCLK Clock Input Timing................................................................................... 707
Figure 23.49 Oscillation Settling Time at RTC Crystal Oscillator Power-on............................ 707
Figure 23.50 SCK Input Clock Timing ..................................................................................... 707
Figure 23.51 SCI I/O Timing in Clock Synchronous Mode ...................................................... 708
Figure 23.52 I/O Port Timing .................................................................................................... 708
Figure 23.53
DREQ Input Timing............................................................................................. 708
Figure 23.54 DRAK Output Timing.......................................................................................... 709
Figure 23.55 TCK Input Timing................................................................................................ 709
Figure 23.56
Figure 23.55 TCK Input Timing................................................................................................ 709
Figure 23.56
TRST Input Timing (Reset Hold)......................................................................... 710
Figure 23.57 UDI Data Transfer Timing ................................................................................... 710
Figure 23.58
Figure 23.58
ASEMD0 Input Timing........................................................................................ 710
Figure 23.59 Output Load Circuit.............................................................................................. 711
Figure 23.60 Load Capacitance vs. Delay Time........................................................................ 712
Figure D.1
Figure 23.60 Load Capacitance vs. Delay Time........................................................................ 712
Figure D.1
Package Dimensions (FP-208C)........................................................................... 758
Figure D.2
Package Dimensions (FP-208E)........................................................................... 759
Figure D.3
Package Dimensions (BP-240A) .......................................................................... 760