Lenovo Intel Xeon Processor E5640 59Y4022 Manual Do Utilizador
Códigos do produto
59Y4022
Register Description
48
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 2
2.11.2
MC_CHANNEL_0_RANK_TIMING_A
MC_CHANNEL_1_RANK_TIMING_A
MC_CHANNEL_2_RANK_TIMING_A
This register contains parameters that specify the rank timing used. All parameters are
in DCLK.
in DCLK.
Device:
4, 5, 6
Function: 0
Offset:
68h
Access as a Dword
Bit
Type
Reset
Value
Description
5
RW
0
RSVD.
4
RW
0
RSVD.
3:2
RW
0
INC_ENTERPWRDWN_RATE. Powerdown rate will be increased during
thermal throttling based on the following configurations.
00: tRANKIDLE (Default)
01: 16
10: 24
11: 32
00: tRANKIDLE (Default)
01: 16
10: 24
11: 32
1
RW
0
DIS_OP_REFRESH. When set, the refresh engine will not issue opportunistic
refresh.
0
RW
0
ASR_PRESENT. When set, indicates DRAMs on this channel can support
Automatic Self Refresh. If the DRAM is not supporting ASR (Auto Self Refresh),
then Self Refresh entry will be delayed until the temperature is below the 2x
refresh temperature.
Device:
4, 5, 6
Function: 0
Offset:
80h
Access as a Dword
Bit
Type
Reset
Value
Description
28:26
RW
0
tddWrTRd. Minimum delay between a write followed by a read to different
DIMMs.
000: 1
001: 2
010: 3
011: 4
100: 5
101: 6
110: 7
111: 8
000: 1
001: 2
010: 3
011: 4
100: 5
101: 6
110: 7
111: 8
25:23
RW
0
tdrWrTRd. Minimum delay between a write followed by a read to different
ranks on the same DIMM.
000: 1
001: 2
010: 3
011: 4
100: 5
101: 6
110: 7
111: 8
000: 1
001: 2
010: 3
011: 4
100: 5
101: 6
110: 7
111: 8