Manual Do Utilizador (59Y4022)índice analítico1 Introduction71.1 References72 Register Description92.1 Register Terminology92.2 Platform Configuration Structure102.3 Device Mapping112.4 Detailed Configuration Space Maps132.5 PCI Standard Registers362.5.1 DID - Device Identification Register372.5.2 RID - Revision Identification Register372.6 Generic Non-core Registers372.6.1 DESIRED_CORES372.6.2 MIRROR_PORT_CTL382.7 SAD - System Address Decoder Registers392.7.1 SAD_MCSEG_BASE392.7.2 SAD_MCSEG_MASK392.7.3 SAD_MESEG_BASE392.7.4 SAD_MESEG_MASK402.8 Intel QPI Link Registers402.8.1 QPI_DEF_RMT_VN_CREDITS_L0 QPI_DEF_RMT_VN_CREDITS_L1402.8.2 QPI_RMT_QPILP1_STAT_L0 QPI_RMT_QPILP1_STAT_L1412.8.3 MIP_PH_CTR_L0 MIP_PH_CTR_L1412.8.4 MIP_PH_PRT_L0 MIP_PH_PRT_L1422.9 Integrated Memory Controller Control Registers422.9.1 MC_SMI_DIMM_ERROR_STATUS432.9.2 MC_SMI__CNTRL432.9.3 MC_MAX_DOD442.9.4 MC_RD_CRDT_INIT452.9.5 MC_SCRUBADDR_HI462.10 Integrated Memory Controller RAS Registers462.10.1 MC_SSRCONTROL462.10.2 MC_SCRUB_CONTROL462.10.3 MC_SSRSTATUS472.11 Integrated Memory Controller Channel Control Registers472.11.1 MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_2_REFRESH_THROTTLE_SUPPORT472.11.2 MC_CHANNEL_0_RANK_TIMING_A MC_CHANNEL_1_RANK_TIMING_A MC_CHANNEL_2_RANK_TIMING_A482.11.3 MC_CHANNEL_0_REFRESH_TIMING MC_CHANNEL_1_REFRESH_TIMING MC_CHANNEL_2_REFRESH_TIMING502.11.4 MC_CHANNEL_0_CKE_TIMING MC_CHANNEL_1_CKE_TIMING MC_CHANNEL_2_CKE_TIMING512.11.5 MC_CHANNEL_0_CKE_TIMING_B MC_CHANNEL_1_CKE_TIMING_B MC_CHANNEL_2_CKE_TIMING_B512.11.6 MC_CHANNEL_0_SCHEDULER_PARAMS MC_CHANNEL_1_SCHEDULER_PARAMS MC_CHANNEL_2_SCHEDULER_PARAMS522.11.7 MC_CHANNEL_0_PAGETABLE_PARAMS2 MC_CHANNEL_1_PAGETABLE_PARAMS2 MC_CHANNEL_2_PAGETABLE_PARAMS2522.12 Memory Thermal Control532.12.1 MC_THERMAL_STATUS0 MC_THERMAL_STATUS1 MC_THERMAL_STATUS2532.12.2 MC_DDR_THERM0_COMMAND0 MC_DDR_THERM0_COMMAND1 MC_DDR_THERM0_COMMAND2532.12.3 MC_DDR_THERM1_COMMAND0 MC_DDR_THERM1_COMMAND1 MC_DDR_THERM1_COMMAND2542.12.4 MC_DDR_THERM0_STATUS0 MC_DDR_THERM0_STATUS1 MC_DDR_THERM0_STATUS2542.12.5 MC_DDR_THERM1_STATUS0 MC_DDR_THERM1_STATUS1 MC_DDR_THERM1_STATUS2553 Functional Description573.1 Integrated Memory Controller573.2 Supported RDIMM Memory Configurations583.2.1 RDIMM 1.5 V Configurations583.2.2 RDIMM 1.35 V Configurations593.3 Supported UDIMM Memory Configurations593.3.1 UDIMM 1.5V Configurations593.3.2 UDIMM 1.35V Configurations613.4 Channel Population Requirements for Memory RAS Modes613.5 Memory Error Signaling623.5.1 Enabling SMI/NMI for Memory Corrected Errors623.5.2 Identifying the Cause of an Interrupt623.6 DDR_THERM# and DDR_THERM2# Pin Response623.7 2X Refresh633.8 Pre-charge Power-Down Slow Exit63Tamanho: 400 KBPáginas: 64Language: EnglishAbrir o manual