Lenovo Intel Xeon Processor E5640 59Y4022 Manual Do Utilizador

53

Status registers for the thermal throttling logic for each channel.

This register contains the command portion of the DDR_THERM# pin functionality (i.e. 
what an assertion of the pin does).

27

RW

0

ENABLEADAPTIVEPAGECLOSE. When set, enables Adaptive Page Closing.

26:18

RW

0

MINPAGECLOSELIMIT. Upper 9 MSBs of a 13-bit threshold limit. When the 

mistake counter falls below this threshold, a less aggressive page close interval 

(larger) is selected.

17:9

RW

0

MAXPAGECLOSELIMIT. Upper 9 bits of a 13-bit threshold limit. When the 

mistake counter exceeds this threshold, a more aggressive page close interval 

(smaller) is selected.

8:0

RW

0

MISTAKECOUNTER. Upper 8 MSBs of a 12-bit counter. This counter adapts 

the interval between assertions of the page close flag. For a less aggressive 

page close, the length of the count interval is increased and vice versa for a 

more aggressive page close policy.

29:4

RO

0

CYCLES_THROTTLED. The number of throttle cycles, in increments of 256 

Dclks, triggered in any rank in the last SAFE_INTERVAL number of ZQs.

3:0

RO

0

RANK_TEMP. The bit[3:0] specifies whether the throttler[3:0] is above 

throttling threshold

. 

3

RW

0

THROTTLE. Force throttling when DDR_THERM# pin is asserted.