Fujitsu SPARC64 V Manual Do Utilizador
6
SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
1.3.2
Instruction Control Unit (IU)
The IU predicts the instruction execution path, fetches instructions on the predicted
path, distributes the fetched instructions to appropriate reservation stations, and
dispatches the instructions to the execution pipeline. The instructions are executed
out of order, and the IU commits the instructions in order. Major blocks are defined
in
path, distributes the fetched instructions to appropriate reservation stations, and
dispatches the instructions to the execution pipeline. The instructions are executed
out of order, and the IU commits the instructions in order. Major blocks are defined
in
1.3.3
Execution Unit (EU)
The EU carries out execution of all integer arithmetic, logical, shift instructions, all
floating-point instructions, and all VIS graphic instructions.
floating-point instructions, and all VIS graphic instructions.
describes the
EU major blocks.
TABLE 1-1
Instruction Control Unit Major Blocks
Name
Description
Instruction fetch pipeline
Five stages: fetch address generation, iTLB access, iTLB match,
I-Cache fetch, and a write to I-buffer.
I-Cache fetch, and a write to I-buffer.
Branch history
16K entries, 4-way set associative.
Instruction buffer
Six entries, 32 bytes/entry.
Reservation station
Six reservation stations to hold instructions until they can
execute:
execute:
RSBR
for branch and the other control-transfer
instructions;
RSA
for load/store instructions;
RSEA
and
RSEB
for
integer arithmetic instructions;
RSFA
and
RSFB
for floating-point
arithmetic and VIS instructions.
Commit stack entries
Sixty-four entries; basically one instruction/entry, to hold
information about instructions issued but not yet committed.
information about instructions issued but not yet committed.
PC
,
nPC
,
CCR
,
FSR
Program-visible registers for instruction execution control.
TABLE 1-2
Execution Unit Major Blocks
Name
Description
General register (gr) renaming
register file (
register file (
GUB
: gr update
buffer)
Thirty-two entries, 8 read ports, 2 write ports
Gr architecture register file (
GPR
) 160 entries, 1 read port, 2 write ports
Floating-point (fr) renaming
register file (
register file (
FUB
: fr update
buffer)
Thirty-two entries, 8 read ports, 2 write ports
Fr architecture register file (
FPR
) Thirty-two entries,
6 read ports, 2 write ports
EU control logic
Controls the instruction execution stages: instruction
selection, register read, and execution.
selection, register read, and execution.