Manuais de utilizador para Fujitsu SPARC64 V

índice analítico

• SPARC JPS1 Implementation Supplement: Fujitsu SPARC64V

  1
  • Fujitsu Limited

    1
  • Release 1.0, 1 July 2002

    1
• Contents

  4
• Overview

  12
  • 1.1 Navigating the SPARC64V Implementation Supplement

    12
  • 1.2 Fonts and Notational Conventions

    12
  • 1.3 The SPARC64V processor

    13
    • 1.3.1 Component Overview

      15
    • 1.3.2 Instruction Control Unit (IU)

      17
    • 1.3.3 Execution Unit (EU)

      17
    • 1.3.4 Storage Unit (SU)

      18
    • 1.3.5 Secondary Cache and External Access Unit (SXU)

      19
• Definitions

  20
• Architectural Overview

  24
• Data Formats

  26
• Registers

  28
  • 5.1 Nonprivileged Registers

    28
    • 5.1.7 Floating-Point State Register (FSR)

      29
    • 5.1.9 Tick (TICK) Register

      30
  • 5.2 Privileged Registers

    30
    • 5.2.6 Trap State (TSTATE) Register

      30
    • 5.2.9 Version (VER) Register

      31
    • 5.2.11 Ancillary State Registers (ASRs)

      31
    • 5.2.12 Registers Referenced Through ASIs

      33
    • 5.2.13 Floating-Point Deferred-Trap Queue (FQ)

      35
    • 5.2.14 IU Deferred-Trap Queue

      35
• Instructions

  36
  • 6.1 Instruction Execution

    36
    • 6.1.1 Data Prefetch

      36
    • 6.1.2 Instruction Prefetch

      37
    • 6.1.3 Syncing Instructions

      38
  • 6.2 Instruction Formats and Fields

    39
  • 6.3 Instruction Categories

    40
    • 6.3.3 Control-Transfer Instructions (CTIs)

      40
    • 6.3.7 Floating-Point Operate (FPop) Instructions

      41
    • 6.3.8 Implementation-Dependent Instructions

      41
  • 6.4 Processor Pipeline

    42
    • 6.4.1 Instruction Fetch Stages

      42
    • 6.4.2 Issue Stages

      44
    • 6.4.3 Execution Stages

      44
    • 6.4.4 Completion Stages

      45
• Traps

  46
  • 7.1 Processor States, Normal and Special Traps

    46
    • 7.1.1 RED_state

      47
    • 7.1.2 error_state

      47
  • 7.2 Trap Categories

    48
    • 7.2.2 Deferred Traps

      48
    • 7.2.4 Reset Traps

      48
    • 7.2.5 Uses of the Trap Categories

      48
  • 7.3 Trap Control

    49
    • 7.3.1 PIL Control

      49
  • 7.4 Trap-Table Entry Addresses

    49
    • 7.4.2 Trap Type (TT)

      49
    • 7.4.4 Details of Supported Traps

      50
  • 7.5 Trap Processing

    50
  • 7.6 Exception and Interrupt Descriptions

    50
    • 7.6.4 SPARC V9 Implementation-Dependent, Optional Traps That Are Mandatory in SPARC JPS1

      50
    • 7.6.5 SPARC JPS1 Implementation-Dependent Traps

      50
• Memory Models

  52
  • 8.1 Overview

    53
  • 8.4 SPARC V9 Memory Model

    53
    • 8.4.5 Mode Control

      53
    • 8.4.6 Synchronizing Instruction and Data Memory

      53
• Instruction Definitions: SPARC64 V Extensions

  56
  • A.4 Block Load and Store Instructions (VIS I)

    58
  • A.12 Call and Link

    60
  • A.24 Implementation-Dependent Instructions

    60
    • A.24.1 Floating-Point Multiply-Add/Subtract

      61
  • A.29 Jump and Link

    64
  • A.30 Load Quadword, Atomic [Physical]

    65
  • A.35 Memory Barrier

    66
  • A.42 Partial Store (VIS I)

    68
  • A.49 Prefetch Data

    68
  • A.51 Read State Register

    69
  • A.70 SHUTDOWN (VIS I)

    69
  • A.70 Write State Register

    70
  • A.71 Deprecated Instructions

    70
    • A.71.10 Store Barrier

      70
• IEEE Std 754-1985 Requirements for SPARC V9

  72
  • B.1 Traps Inhibiting Results

    72
  • B.6 Floating-Point Nonstandard Mode

    72
    • B.6.1 fp_exception_other Exception (ftt=unfinished_FPop)

      73
    • B.6.2 Operation Under FSR.NS = 1

      76
• Implementation Dependencies

  80
  • C.1 Definition of an Implementation Dependency

    80
  • C.2 Hardware Characteristics

    81
  • C.3 Implementation Dependency Categories

    81
  • C.4 List of Implementation Dependencies

    81
• Formal Specification of the Memory Models

  92
• Opcode Maps

  94
• Memory Management Unit

  96
  • F.1 Virtual Address Translation

    96
  • F.2 Translation Table Entry (TTE)

    97
    • F.3.3 TSB Organization

      99
    • F.4.2 TSB Pointer Formation

      99
  • F.5 Faults and Traps

    100
  • F.8 Reset, Disable, and RED_state Behavior

    102
  • F.10 Internal Registers and ASI operations

    103
    • F.10.1 Accessing MMU Registers

      103
    • F.10.4 I/D TLB Data In, Data Access, and Tag Read Registers

      104
    • F.10.7 I/D TSB Extension Registers

      108
    • F.10.9 I/D Synchronous Fault Status Registers (I-SFSR, D-SFSR)

      108
  • F.11 MMU Bypass

    115
    • F.11.10 TLB Replacement Policy

      116
• Assembly Language Syntax

  118
• Software Considerations

  120
• Extending the SPARC V9 Architecture

  122
• Changes from SPARC V8 to SPARC V9

  124
• Programming with the Memory Models

  126
• Address Space Identifiers

  128
  • L.3 SPARC64 V ASI Assignments

    128
    • L.3.2 Special Memory Access ASIs

      130
  • L.4 Barrier Assist for Parallel Processing

    132
    • L.4.1 Interface Definition

      132
    • L.4.2 ASI Registers

      133
• Cache Organization

  136
  • M.1 Cache Types

    136
    • M.1.1 Level-1 Instruction Cache (L1I Cache)

      137
    • M.1.2 Level-1 Data Cache (L1D Cache)

      138
    • M.1.3 Level-2 Unified Cache (L2 Cache)

      138
  • M.2 Cache Coherency Protocols

    139
  • M.3 Cache Control/Status Instructions

    139
    • M.3.1 Flush Level-1 Instruction Cache (ASI_FLUSH_L1I)

      140
    • M.3.2 Level-2 Cache Control Register (ASI_L2_CTRL)

      141
    • M.3.3 L2 Diagnostics Tag Read (ASI_L2_DIAG_TAG_READ)

      141
    • M.3.4 L2 Diagnostics Tag Read Registers (ASI_L2_DIAG_TAG_READ_REG)

      142
• Interrupt Handling

  144
  • N.1 Interrupt Dispatch

    144
  • N.2 Interrupt Receive

    146
  • N.3 Interrupt Global Registers

    147
  • N.4 Interrupt-Related ASR Registers

    147
    • N.4.2 Interrupt Vector Dispatch Register

      147
    • N.4.3 Interrupt Vector Dispatch Status Register

      147
    • N.4.5 Interrupt Vector Receive Register

      147
• Reset, RED_state, and error_state

  148
  • O.1 Reset Types

    148
    • O.1.1 Power-on Reset (POR)

      148
    • O.1.2 Watchdog Reset (WDR)

      149
    • O.1.3 Externally Initiated Reset (XIR)

      149
    • O.1.4 Software-Initiated Reset (SIR)

      149
  • O.2 RED_state and error_state

    150
    • O.2.1 RED_state

      151
    • O.2.2 error_state

      151
    • O.2.3 CPU Fatal Error state

      152
  • O.3 Processor State after Reset and in RED_state

    152
    • O.3.1 Operating Status Register (OPSR)

      157
    • O.3.2 Hardware Power-On Reset Sequence

      158
    • O.3.3 Firmware Initialization Sequence

      158
• Error Handling

  160
  • P.1 Error Classification

    160
    • P.1.1 Fatal Error

      160
    • P.1.2 error_state Transition Error

      161
    • P.1.3 Urgent Error

      161
    • P.1.4 Restrainable Error

      163
  • P.2 Action and Error Control

    164
    • P.2.1 Registers Related to Error Handling

      164
    • P.2.2 Summary of Actions Upon Error Detection

      165
    • P.2.3 Extent of Automatic Source Data Correction for Correctable Error

      168
    • P.2.4 Error Marking for Cacheable Data Error

      168
    • P.2.5 ASI_EIDR

      172
    • P.2.6 Control of Error Action (ASI_ERROR_CONTROL)

      172
  • P.3 Fatal Error and error_state Transition Error

    174
    • P.3.1 ASI_STCHG_ERROR_INFO

      174
    • P.3.2 Fatal Error Types

      175
    • P.3.3 Types of error_state Transition Errors

      175
  • P.4 Urgent Error

    176
    • P.4.1 URGENT ERROR STATUS (ASI_UGESR)

      176
    • P.4.2 Action of async_data_error (ADE) Trap

      179
    • P.4.3 Instruction End-Method at ADE Trap

      181
    • P.4.4 Expected Software Handling of ADE Trap

      182
  • P.5 Instruction Access Errors

    184
  • P.6 Data Access Errors

    184
  • P.7 Restrainable Errors

    185
    • P.7.1 ASI_ASYNC_FAULT_STATUS (ASI_AFSR)

      185
    • P.7.2 ASI_ASYNC_FAULT_ADDR_D1

      188
    • P.7.3 ASI_ASYNC_FAULT_ADDR_U2

      189
    • P.7.4 Expected Software Handling of Restrainable Errors

      190
  • P.8 Handling of Internal Register Errors

    192
    • P.8.1 Register Error Handling (Excluding ASRs and ASI Registers)

      192
    • P.8.2 ASR Error Handling

      193
    • P.8.3 ASI Register Error Handling

      194
  • P.9 Cache Error Handling

    199
    • P.9.1 Handling of a Cache Tag Error

      199
    • P.9.2 Handling of an I1 Cache Data Error

      201
    • P.9.3 Handling of a D1 Cache Data Error

      201
    • P.9.4 Handling of a U2 Cache Data Error

      203
    • P.9.5 Automatic Way Reduction of I1 Cache, D1 Cache, and U2 Cache

      204
  • P.10 TLB Error Handling

    206
    • P.10.1 Handling of TLB Entry Errors

      206
    • P.10.2 Automatic Way Reduction of sTLB

      207
  • P.11 Handling of Extended UPA Bus Interface Error

    208
    • P.11.1 Handling of Extended UPA Address Bus Error

      208
    • P.11.2 Handling of Extended UPA Data Bus Error

      208
• Performance Instrumentation

  212
  • Q.1 Performance Monitor Overview

    212
    • Q.1.1 Sample Pseudocodes

      212
  • Q.2 Performance Monitor Description

    214
    • Q.2.1 Instruction Statistics

      215
    • Q.2.2 Trap-Related Statistics

      217
    • Q.2.3 MMU Event Counters

      218
    • Q.2.4 Cache Event Counters

      219
    • Q.2.5 UPA Event Counters

      221
    • Q.2.6 Miscellaneous Counters

      222
• UPA Programmer’s Model

  224
  • R.1 Mapping of the CPU’s UPA Port Slave Area

    224
  • R.2 UPA PortID Register

    225
  • R.3 UPA Config Register

    226
• Summary of Differences between SPARC64 V and UltraSPARC-III

  230
• Bibliography

  234
  • General References

    234