Fujitsu SPARC64 V Manual Do Utilizador
F. A P P E N D I X
213
R
UPA Programmer ’s Model
This chapter describes the programmers model of the UPA interface of the
SPARC64 V. The registers for the UPA interface and the access method for those
registers are described. The appendix contains the following sections:
SPARC64 V. The registers for the UPA interface and the access method for those
registers are described. The appendix contains the following sections:
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R.1
Mapping of the CPU’s UPA Port Slave
Area
Area
shows the mapping of the CPU’s UPA port slave area.
TABLE R-1
CPU’s UPA Port Slave Area Mapping
Relative Address
(Hex)
(Hex)
Length
Possible Access
Contents
0 0000 0000
8
Slave read from other
UPA port
UPA port
UPA PortID Register; defined in
Section R.2.
Section R.2.
0 0000 0008
~ 1 FFFF FFFF
~ 1 FFFF FFFF
--
None
Nothing. Write is ignored and
undefined value is read.
undefined value is read.