Fujitsu SPARC64 V Manual Do Utilizador
Release 1.0, 1 July 2002
F. Chapter 8
Memory Models
43
corresponding locations in all instruction caches; references to any instruction cache
cause corresponding modified data to be flushed and corresponding unmodified
data to be invalidated from all data caches. The flush operation is still operative in
SPARC64 V, however.
cause corresponding modified data to be flushed and corresponding unmodified
data to be invalidated from all data caches. The flush operation is still operative in
SPARC64 V, however.
Since the
FLUSH
instruction synchronizes the processor, the total latency varies
depending on the situation in SPARC64 V. Assuming all prior instructions are
completed, the latency of
completed, the latency of
FLUSH
is 18 CPU cycles.