Fujitsu SPARC64 V Manual Do Utilizador
70
SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
C.2
Hardware Characteristics
Please refer to Section C.2 of Commonality.
C.3
Implementation Dependency Categories
Please refer to Section C.3 of Commonality.
C.4
List of Implementation Dependencies
provides a complete list of how each implementation dependency is
treated in the
SPARC64 V
implementation.
TABLE C-1
SPARC64 V Implementation Dependencies (1 of 11)
Nbr
SPARC64 V Implementation Notes
Page
1
Software emulation of instructions
The operating system emulates all instructions that generate
The operating system emulates all instructions that generate
illegal_instruction
or
unimplemented_FPop
exceptions.
—
2
Number of IU registers
SPARC64 V
supports eight register windows (
NWINDOWS
= 8).
SPARC64 V supports an additional two global register sets (Interrupt
globals and MMU globals) for a total of 160 integer registers.
globals and MMU globals) for a total of 160 integer registers.
—
3
Incorrect IEEE Std 754-1985 results
See Section B.6, Floating-Point Nonstandard Mode, on page 61 for details.
See Section B.6, Floating-Point Nonstandard Mode, on page 61 for details.
4–5
Reserved.
6
I/O registers privileged status
This dependency is beyond the scope of this publication. It should be
defined in each system that uses
This dependency is beyond the scope of this publication. It should be
defined in each system that uses
SPARC64 V
.
—
7
I/O register definitions
This dependency is beyond the scope of this publication. It should be
defined in each system that uses
This dependency is beyond the scope of this publication. It should be
defined in each system that uses
SPARC64 V
.
—
8
RDASR
/
WRASR
target registers
See A.50 and A.70 in Commonality for details of implementation-dependent
RDASR
/
WRASR
instructions.
—