Cypress CY7C6431x Manual Do Utilizador

Document Number: 001-12394 Rev *G

Page 21 of 28

 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.  

 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.  

T

RSCLK

Rise Time of SCLK 

1

–

20

ns

T

FSCLK

Fall Time of SCLK 

1

–

20

ns

T

SSCLK

Data Setup Time to Falling Edge of SCLK

40

–

–

ns

T

HSCLK

Data Hold Time from Falling Edge of SCLK

40

–

–

ns

F

SCLK

Frequency of SCLK

0

–

8

MHz

T

ERASEB

Flash Erase Time (Block)

–

–

18

ms

T

WRITE

Flash Block Write Time

–

–

25

ms

T

DSCLK1

Data Out Delay from Falling Edge of SCLK, Vdd > 3.6V

–

–

60

ns

T

DSCLK2

Data Out Delay from Falling Edge of SCLK, 3.0V<Vdd<3.6V

–

–

85

ns

F

SPIM

Maximum Input Clock Frequency Selection, Master

–

–

12

MHz

F

SPIS

Maximum Input Clock Frequency Selection, Slave

–

–

12

MHz

T

SS

Width of SS_ Negated Between Transmissions

50

–

–

ns

14. Output clock frequency is half of input clock rate.