Fujitsu FR81S Manual Do Utilizador
CHAPTER 21: 32-BIT FREE-RUN TIMER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT FREE-RUN TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
15
[bit3 to bit0] CLK3 to CLK0 : Clock frequency selection (when internal clock is selected)
CLK3 CLK2 CLK1 CLK0
Clock frequency selection ( F
PCLK
: Peripheral clock (PCLK))
Count
clock
F
PCLK
=16MHz
F
PCLK
=8MHz
F
PCLK
=4MHz
F
PCLK
=1MHz
0
0
0
0
1/F
PCLK
62.5ns
125ns
0.25μs
1μs
0
0
0
1
2/F
PCLK
125ns
0.25μs
0.5μs
2μs
0
0
1
0
4/F
PCLK
0.25μs
0.5μs
1μs
4μs
0
0
1
1
8/F
PCLK
0.5μs
1μs
2μs
8μs
0
1
0
0
16/F
PCLK
1μs
2μs
4μs
16μs
0
1
0
1
32/F
PCLK
2μs
4μs
8μs
32μs
0
1
1
0
64/F
PCLK
4μs
8μs
16μs
64μs
0
1
1
1
128/F
PCLK
8μs
16μs
32μs
128μs
1
0
0
0
256/F
PCLK
16μs
32μs
64μs
256μs
Other settings prohibit
-
-
-
-
-
⋅
The frequency is changed at the same time as the setting change to the clock frequency selection bit. If
internal clock is selected as the count clock of the free-run timer (clock selection bit (ECKE= "0")),
change the setting while other peripheral modules (output compare and input capture) using the free-run
timer output are inactive.
⋅
When the free-run timer is used as compare data for the output compare, the free-run timer clock
frequency cannot be set as CLK[3:0]= "0000
B
".
MB91520 Series
MN705-00010-1v0-E
810