Intel 253668-032US Manual Do Utilizador

Vol. 3 4-21

PAGING

A reference using a linear address that is successfully translated to a physical 
address is performed only if allowed by the access rights of the translation; see 
Section 4.6.
Figure 4-7 gives a summary of the formats of CR3 and the paging-structure entries 
with PAE paging. For the paging structure entries, it identifies separately the format 
of entries that map pages, those that reference other paging structures, and those 

Table 4-10.  Format of a PAE Page-Directory Entry that References a Page Table

Bit 

Position(s)

Contents

0 (P)

Present; must be 1 to reference a page table

1 (R/W)

Read/write; if 0, writes may not be allowed to the 2-MByte region controlled by 

this entry (depends on CPL and CR0.WP; see Section 4.6)

2 (U/S)

User/supervisor; if 0, accesses with CPL=3 are not allowed to the 2-MByte region 

controlled by this entry (see Section 4.6)

3 (PWT)

Page-level write-through; indirectly determines the memory type used to access 

the page table referenced by this entry (see Section 4.9)

4 (PCD)

Page-level cache disable; indirectly determines the memory type used to access 

the page table referenced by this entry (see Section 4.9)

5 (A)

Accessed; indicates whether this entry has been used for linear-address 

translation (see Section 4.8)

6

Ignored

7 (PS)

Page size; must be 0 (otherwise, this entry maps a 2-MByte page; see Table 4-9)

11:8

Ignored

M–1:12

Physical address of 4-KByte aligned page table referenced by this entry

62:M

Reserved (must be 0)

63 (XD)

If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed 

from the 2-MByte region controlled by this entry; see Section 4.6); otherwise, 

reserved (must be 0)