Intel 253668-032US Manual Do Utilizador

4-22 Vol. 3

PAGING

Table 4-11. Format of a PAE Page-Table Entry that Maps a 4-KByte Page

Bit

Position(s)

Contents

0 (P)

Present; must be 1 to map a 4-KByte page

1 (R/W)

Read/write; if 0, writes may not be allowed to the 4-KByte page referenced by this

entry (depends on CPL and CR0.WP; see Section 4.6)

2 (U/S)

User/supervisor; if 0, accesses with CPL=3 are not allowed to the 4-KByte page

referenced by this entry (see Section 4.6)

3 (PWT)

Page-level write-through; indirectly determines the memory type used to access

the 4-KByte page referenced by this entry (see Section 4.9)

4 (PCD)

Page-level cache disable; indirectly determines the memory type used to access

the 4-KByte page referenced by this entry (see Section 4.9)

5 (A)

Accessed; indicates whether software has accessed the 4-KByte page referenced

by this entry (see Section 4.8)

6 (D)

Dirty; indicates whether software has written to the 4-KByte page referenced by

7 (PAT)

If the PAT is supported, indirectly determines the memory type used to access the

4-KByte page referenced by this entry (see Section 4.9); otherwise, reserved

(must be 0)

8 (G)

Global; if CR4.PGE = 1, determines whether the translation is global (see Section

4.10); ignored otherwise

11:9

Ignored

M–1:12

Physical address of the 4-KByte page referenced by this entry

62:M

Reserved (must be 0)

63 (XD)

If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed

from the 4-KByte page controlled by this entry; see Section 4.6); otherwise,

reserved (must be 0)

NOTES:

1. See Section 4.1.4 for how to determine whether the PAT is supported.