Intel 253668-032US Manual Do Utilizador
Vol. 3 4-25
PAGING
•
A 4-KByte naturally aligned page-directory-pointer table is located at the
physical address specified in bits 51:12 of the PML4E (see Table 4-13). A page-
directory-pointer table comprises 512 64-bit entries (PDPTEs). A PDPTE is
selected using the physical address defined as follows:
— Bits 51:12 are from the PML4E.
— Bits 11:3 are bits 38:30 of the linear address.
— Bits 2:0 are all 0.
Because a PDPTE is identified using bits 47:30 of the linear address, it controls
access to a 1-GByte region of the linear-address space.
physical address specified in bits 51:12 of the PML4E (see Table 4-13). A page-
directory-pointer table comprises 512 64-bit entries (PDPTEs). A PDPTE is
selected using the physical address defined as follows:
— Bits 51:12 are from the PML4E.
— Bits 11:3 are bits 38:30 of the linear address.
— Bits 2:0 are all 0.
Because a PDPTE is identified using bits 47:30 of the linear address, it controls
access to a 1-GByte region of the linear-address space.
•
A 4-KByte naturally aligned page directory is located at the physical address
specified in bits 51:12 of the PDPTE (see Table 4-14). A page directory comprises
512 64-bit entries (PDEs). A PDE is selected using the physical address defined as
follows:
— Bits 51:12 are from the PDPTE.
— Bits 11:3 are bits 29:21 of the linear address.
— Bits 2:0 are all 0.
specified in bits 51:12 of the PDPTE (see Table 4-14). A page directory comprises
512 64-bit entries (PDEs). A PDE is selected using the physical address defined as
follows:
— Bits 51:12 are from the PDPTE.
— Bits 11:3 are bits 29:21 of the linear address.
— Bits 2:0 are all 0.
Figure 4-8. Linear-Address Translation to a 4-KByte Page using IA-32e Paging
Directory Ptr
PTE
Linear Address
Page Table
PDPTE
CR3
39 38
Pointer Table
9
9
40
12
9
40
4-KByte Page
Offset
Physical Addr
PDE with PS=0
Table
0
11
12
20
21
Directory
30 29
Page-Directory-
Page-Directory
PML4
47
9
PML4E
40
40
40