Intel 253668-032US Manual Do Utilizador
4-24 Vol. 3
PAGING
bits corresponds to 4 PBytes, linear addresses are limited to 48 bits; at most 256
TBytes of linear-address space may be accessed at any given time.
IA-32e paging uses a hierarchy of paging structures to produce a translation for a
linear address. CR3 is used to locate the first paging-structure, the PML4 table.
Table 4-12 illustrates how CR3 is used with IA-32e paging.
TBytes of linear-address space may be accessed at any given time.
IA-32e paging uses a hierarchy of paging structures to produce a translation for a
linear address. CR3 is used to locate the first paging-structure, the PML4 table.
Table 4-12 illustrates how CR3 is used with IA-32e paging.
IA-32e paging may map linear addresses to either 4-KByte pages or 2-MByte pages.
Figure 4-8 illustrates the translation process when it produces a 4-KByte page;
Figure 4-9 covers the case of a 2-MByte page. The following items describe the
IA-32e paging process in more detail as well has how the page size is determined:
Figure 4-8 illustrates the translation process when it produces a 4-KByte page;
Figure 4-9 covers the case of a 2-MByte page. The following items describe the
IA-32e paging process in more detail as well has how the page size is determined:
•
A 4-KByte naturally aligned PML4 table is located at the physical address
specified in bits 51:12 of CR3 (see Table 4-12). A PML4 table comprises 512 64-
bit entries (PML4Es). A PML4E is selected using the physical address defined as
follows:
— Bits 51:12 are from CR3.
— Bits 11:3 are bits 47:39 of the linear address.
— Bits 2:0 are all 0.
Because a PML4E is identified using bits 47:39 of the linear address, it controls
access to a 512-GByte region of the linear-address space.
specified in bits 51:12 of CR3 (see Table 4-12). A PML4 table comprises 512 64-
bit entries (PML4Es). A PML4E is selected using the physical address defined as
follows:
— Bits 51:12 are from CR3.
— Bits 11:3 are bits 47:39 of the linear address.
— Bits 2:0 are all 0.
Because a PML4E is identified using bits 47:39 of the linear address, it controls
access to a 512-GByte region of the linear-address space.
1. If MAXPHYADDR < 52, bits in the range 51:MAXPHYADDR will be 0 in any physical address used
by IA-32e paging. (The corresponding bits are reserved in the paging-structure entries.) See Sec-
tion 4.1.4 for how to determine MAXPHYADDR.
Table 4-12. Use of CR3 with IA-32e Paging
Bit
Position(s)
Contents
2:0
Ignored
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access
the PML4 table during linear-address translation (see Section 4.9)
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access
the PML4 table during linear-address translation (see Section 4.9)
11:5
Ignored
M–1:12
Physical address of the 4-KByte aligned PML4 table used for linear-address
translation
1
NOTES:
1. M is an abbreviation for MAXPHYADDR, which is at most 52; see Section 4.1.4.
63:M
Reserved (must be 0)