Renesas R5S72625 Manual Do Utilizador
Section 9 Bus State Controller
Page 308 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Table 9.9
Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address
Multiplex Output (1)-1
Multiplex Output (1)-1
Setting
BSZ
[1:0]
[1:0]
A2/3
ROW
[1:0]
ROW
[1:0]
A2/3
COL
[1:0]
COL
[1:0]
11 (16 bits)
00 (11 bits)
00 (8 bits)
Output Pin of
This LSI
This LSI
Row Address
Output Cycle
Output Cycle
Column Address
Output Cycle
Output Cycle
SDRAM Pin
Function
A17 A25 A17
Unused
A16 A24 A16
A15 A23 A15
A14 A22 A14
A13 A21 A21
A12 A20*
2
A20*
2
A11 (BA0)
Specifies bank
A11 A19 L/H*
1
A10/AP Specifies
address/precharge
A10 A18 A10
A9
Address
A9 A17 A9
A8
A8 A16 A8
A7
A7 A15 A7
A6
A6 A14 A6
A5
A5 A13 A5
A4
A4 A12 A4
A3
A3 A11 A3
A2
A2 A10 A2
A1
A1 A9 A1
A0
A0 A8 A0
Unused
Example of connected memory
16-Mbit product (512 Kwords
16 bits 2 banks, column 8 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2. Bank address specification