Renesas R5S72625 Manual Do Utilizador
Section 9 Bus State Controller
Page 310 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Table 9.10 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address
Multiplex Output (2)-1
Setting
BSZ
[1:0]
[1:0]
A2/3
ROW
[1:0]
ROW
[1:0]
A2/3
COL
[1:0]
COL
[1:0]
10 (16 bits)
01 (12 bits)
01 (9 bits)
Output Pin of
This LSI
This LSI
Row Address
Output Cycle
Output Cycle
Column Address
Output Cycle
Output Cycle
SDRAM Pin
Function
A17 A26 A17
Unused
A16 A25 A16
A15 A24 A15
A14 A23*
2
A23*
2
A13
(BA1)
Specifies bank
A13 A22*
2
A22*
2
A12
(BA0)
A12 A21 A12
A11
Address
A11 A20 L/H*
1
A10/AP
Specifies
address/precharge
address/precharge
A10 A19 A10
A9
Address
A9 A18 A9
A8
A8 A17 A8
A7
A7 A16 A7
A6
A6 A15 A6
A5
A5 A14 A5
A4
A4 A13 A4
A3
A3 A12 A3
A2
A2 A11 A2
A1
A1 A10 A1
A0
A0 A9 A0
Unused
Example of connected memory
128-Mbit product (2 Mwords
16 bits 4 banks, column 9 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2.
Bank
address
specification