Renesas R5S72622 Manual Do Utilizador
Section 33 Power-Down Modes
Page 1808 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
(2) Canceling Software Standby Mode
Software standby mode is canceled by interrupts (NMI or IRQ) or a reset (power-on reset). Clock
signal starts to be output from the CKIO pin.
signal starts to be output from the CKIO pin.
Canceling by an interrupt
When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit
(NMIE) in interrupt control register 0 (ICR0) of the interrupt controller) or the falling edge or
rising edge of an IRQ pin (IRQ7 to IRQ0) (selected by the IRQn sense select bits (IRQn1S and
IRQn0S) in interrupt control register 1 (ICR1) of the interrupt controller) is detected, clock
oscillation is started. This clock pulse is supplied only to the oscillation settling counter
(watchdog timer) used to count the oscillation settling time.
(NMIE) in interrupt control register 0 (ICR0) of the interrupt controller) or the falling edge or
rising edge of an IRQ pin (IRQ7 to IRQ0) (selected by the IRQn sense select bits (IRQn1S and
IRQn0S) in interrupt control register 1 (ICR1) of the interrupt controller) is detected, clock
oscillation is started. This clock pulse is supplied only to the oscillation settling counter
(watchdog timer) used to count the oscillation settling time.
After the elapse of the time set in the clock select bits (CKS[2:0]) in the watchdog timer
control/status register (WTCSR) of the watchdog timer before the transition to software
standby mode, the watchdog timer overflow occurs. Since this overflow indicates that the
clock has been stabilized, the clock pulse will be supplied to the entire chip after this overflow.
Software standby mode is thus cleared and NMI interrupt exception handling (IRQ interrupt
exception handling in case of IRQ) is started. If the priority level of the generated interrupt is
equal to or lower than the interrupt mask level specified in the status register (SR) of the CPU,
the interrupt request is not accepted and software standby mode is not canceled.
control/status register (WTCSR) of the watchdog timer before the transition to software
standby mode, the watchdog timer overflow occurs. Since this overflow indicates that the
clock has been stabilized, the clock pulse will be supplied to the entire chip after this overflow.
Software standby mode is thus cleared and NMI interrupt exception handling (IRQ interrupt
exception handling in case of IRQ) is started. If the priority level of the generated interrupt is
equal to or lower than the interrupt mask level specified in the status register (SR) of the CPU,
the interrupt request is not accepted and software standby mode is not canceled.
When canceling software standby mode by the NMI interrupt or IRQ interrupt, set the
CKS[2:0] bits so that the watchdog timer overflow period will be equal to or longer than the
oscillation settling time.
CKS[2:0] bits so that the watchdog timer overflow period will be equal to or longer than the
oscillation settling time.
The clock output phase of the CKIO pin may be unstable immediately after detecting an
interrupt and until software standby mode is canceled. When software standby mode is
canceled by the falling edge of the NMI pin, the NMI pin should be high when software
standby mode is entered (when the clock pulse stops) and should be low when software
standby mode is canceled (when the clock is initiated after the oscillation settling). When
software standby mode is canceled by the rising edge of the NMI pin, the NMI pin should be
low when software standby mode is entered (when the clock pulse stops) and should be high
when software standby mode is canceled (when the clock is initiated after the oscillation
settling) (This is the same with the IRQ pin.)
interrupt and until software standby mode is canceled. When software standby mode is
canceled by the falling edge of the NMI pin, the NMI pin should be high when software
standby mode is entered (when the clock pulse stops) and should be low when software
standby mode is canceled (when the clock is initiated after the oscillation settling). When
software standby mode is canceled by the rising edge of the NMI pin, the NMI pin should be
low when software standby mode is entered (when the clock pulse stops) and should be high
when software standby mode is canceled (when the clock is initiated after the oscillation
settling) (This is the same with the IRQ pin.)
Canceling by a reset
When the
RES pin is driven low, software standby mode is canceled and the LSI enters the
power-on reset state. After that, if the
RES pin is driven high, the power-on reset exception
handling is started.
Keep the
RES pin low until the clock oscillation settles. The internal clock will continue to be
output to the CKIO pin.