Renesas R5S72622 Manual Do Utilizador

 

 

 

 

 

Section 9   Bus State Controller 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 339 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

The low-power SDRAM can be accessed using the same protocol as the normal SDRAM.  

The differences between the low-power SDRAM and normal SDRAM are that partial refresh 
takes place that puts only a part of the SDRAM in the self-refresh state during the self-refresh 
function, and that power consumption is low during refresh under user conditions such as the 
operating temperature. The partial refresh is effective in systems in which the data in a work area 
other than the specific area can be lost without severe repercussions. For details, please refer to the 
Data Sheet for the low-power SDRAM to be used. 

The low-power SDRAM supports the extension mode register in addition to the mode registers as 
the normal SDRAM. This LSI supports issuing of the extension mode register write command 
(EMRS). 

The EMRS command is issued according to the conditions specified in table below. For example, 
if data H'0YYYYYYY is written to address H'FFFC5XX0 in longword, the commands are issued 
to the CS3 space in the following sequence: PALL -> REF 

 8 -> MRS -> EMRS. In this case, the 

MRS and EMRS issue addresses are H'0000XX0 and H'YYYYYYY, respectively. If data 
H'1YYYYYYY is written to address H'FFFC5XX0 in longword, the commands are issued to the 
CS3 space in the following sequence: PALL -> MRS -> EMRS. 

CS2 MRS 

H'FFFC4XX0

H'******** 16 

bits H'0000XX0 

 

CS3 MRS 

H'FFFC5XX0

H'******** 16 

bits H'0000XX0 

 

CS2 MRS + EMRS 

(with refresh) 

H'FFFC4XX0

H'0YYYYYYY 32 bits 

H'0000XX0 

H'YYYYYYY 

CS3 MRS + EMRS 

(with refresh) 

H'FFFC5XX0

H'0YYYYYYY 32 bits 

H'0000XX0 

H'YYYYYYY 

CS2 MRS + EMRS 

(without refresh) 

H'FFFC4XX0

H'1YYYYYYY 32 bits 

H'0000XX0 

H'YYYYYYY 

CS3 MRS + EMRS 

(without refresh) 

H'FFFC5XX0

H'1YYYYYYY 32 bits 

H'0000XX0 

H'YYYYYYY