Renesas R5S72622 Manual Do Utilizador

 

 

 

 

 

Section 9   Bus State Controller 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 341 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

  Deep power-down mode 

The low-power SDRAM supports the deep power-down mode as a low-power consumption 
mode. In the partial self-refresh function, self-refresh is performed on a specific area. In the 
deep power-down mode, self-refresh will not be performed on any memory area. This mode is 
effective in systems where all of the system memory areas are used as work areas. 

 
If the RMODE bit in the SDCR is set to 1 while the DEEP and RFSH bits in the SDCR are set to 
1, the low-power SDRAM enters the deep power-down mode. If the RMODE bit is cleared to 0, 
the CKE signal is pulled high to cancel the deep power-down mode. Before executing an access 
after returning from the deep power-down mode, the power-up sequence must be re-executed. 

Tpw

Tp

Tdpd

Trc

Hi-Z

Trc

Trc

Trc

Trc

CKIO

CKE

A25 to A0

CSn

RD/

WR

RAS

DQMx

D15 to D0

BS

DACKn*

2

A12/A11*

1

CAS

Notes:  1. Address pin to be connected to pin A10 of SDRAM.

             2. The waveform for DACKn is when active low is specified.