Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Ficha De Dados
Códigos do produto
P4X-UPE3210-316-6M1333
DRAM Controller Registers (D0:F0)
118
Datasheet
5.2.25
C1CYCTRKWR—Channel 1 CYCTRK WR
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 656–657h
Default Value:
0000h
Access:
RW
Size:
16 bits
Channel 1 CYCTRK WR registers.
5.2.26
C1CYCTRKRD—Channel 1 CYCTRK READ
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 658–65Ah
Default Value:
000000h
Access:
RW, RO
Size:
24 bits
Channel 1 CYCTRK READ registers.
Bit
Access
Default
Value
Description
15:12
RW
0h
ACT To Write Delay (C1sd_cr_act_wr): This field indicates the minimum
allowed spacing (in DRAM clocks) between the ACT and WRITE commands to the
same rank-bank. This field corresponds to t
allowed spacing (in DRAM clocks) between the ACT and WRITE commands to the
same rank-bank. This field corresponds to t
RCD_wr
in the DDR Specification.
11:8
RW
0h
Same Rank Write To Write Delayed (C1sd_cr_wrsr_wr): This field register
indicates the minimum allowed spacing (in DRAM clocks) between two WRITE
commands to the same rank.
indicates the minimum allowed spacing (in DRAM clocks) between two WRITE
commands to the same rank.
7:4
RW
0h
Different Rank Write to Write Delay (C1sd_cr_wrdr_wr): This field
indicates the minimum allowed spacing (in DRAM clocks) between two WRITE
commands to different ranks. This field corresponds to t
indicates the minimum allowed spacing (in DRAM clocks) between two WRITE
commands to different ranks. This field corresponds to t
WR_WR
in the DDR
Specification.
3:0
RW
0h
READ To WRTE Delay (C1sd_cr_rd_wr): This field indicates the minimum
allowed spacing (in DRAM clocks) between the READ and WRITE commands.
This field corresponds to t
allowed spacing (in DRAM clocks) between the READ and WRITE commands.
This field corresponds to t
RD_WR
.
Bit
Access
Default
Value
Description
23:21
RO
0h
Reserved
20:17
RW
0h
Min ACT To READ Delayed (C1sd_cr_act_rd): This field indicates the
minimum allowed spacing (in DRAM clocks) between the ACT and READ
commands to the same rank-bank. This field Corresponds to t
minimum allowed spacing (in DRAM clocks) between the ACT and READ
commands to the same rank-bank. This field Corresponds to t
RCD_rd
in the DDR
Specification
16:12
RW
00000b
Same Rank Write To READ Delayed (C1sd_cr_wrsr_rd): This field indicates
the minimum allowed spacing (in DRAM clocks) between the WRITE and READ
commands to the same rank. This field corresponds to t
the minimum allowed spacing (in DRAM clocks) between the WRITE and READ
commands to the same rank. This field corresponds to t
WTR
in the DDR
Specification.
11:8
RW
0000b
Different Ranks Write To READ Delayed (C1sd_cr_wrdr_rd): This field
indicates the minimum allowed spacing (in DRAM clocks) between the WRITE
and READ commands to different ranks. This field corresponds to t
indicates the minimum allowed spacing (in DRAM clocks) between the WRITE
and READ commands to different ranks. This field corresponds to t
WR_RD
in the
DDR Specification.
7:4
RW
0000b
Same Rank Read To Read Delayed (C1sd_cr_rdsr_rd): This field indicates
the minimum allowed spacing (in DRAM clocks) between two READ commands to
the same rank.
the minimum allowed spacing (in DRAM clocks) between two READ commands to
the same rank.
3:0
RW
0000b
Different Ranks Read To Read Delayed (C1sd_cr_rddr_rd): This field
indicates the minimum allowed spacing (in DRAM clocks) between two READ
commands to different ranks. This field corresponds to t
indicates the minimum allowed spacing (in DRAM clocks) between two READ
commands to different ranks. This field corresponds to t
RD_RD
.