Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Ficha De Dados
Códigos do produto
P4X-UPE3210-316-6M1333
Datasheet
119
DRAM Controller Registers (D0:F0)
5.2.27
C1CKECTRL—Channel 1 CKE Control
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 660–663h
Default Value:
00000800h
Access:
RO, RW/L, RW
Size:
32 bits
Channel 1 CKE Control registers.
Bit
Access
Default
Value
Description
31:28
RO
0h
Reserved
27
RW
0b
Start the Self-Refresh Exit Sequence (sd1_cr_srcstart): This bit indicates
the request to start the self-refresh exit sequence
the request to start the self-refresh exit sequence
26:24
RW
000b
CKE Pulse Width Requirement in High Phase (sd1_cr_cke_pw_hl_safe):
This bit indicates CKE pulse width requirement in high phase. This field
Corresponds to t
This bit indicates CKE pulse width requirement in high phase. This field
Corresponds to t
CKE
(high) in the DDR Specification.
23
RW/L
0b
Rank 3 Population (sd1_cr_rankpop3):
1 = Rank 3 populated
0 = Rank 3 not populated
This register is locked by ME stolen Memory lock.
1 = Rank 3 populated
0 = Rank 3 not populated
This register is locked by ME stolen Memory lock.
22
RW/L
0b
Rank 2 Population (sd1_cr_rankpop2):
1 = Rank 2 populated
0 = Rank 2 not populated
This register is locked by ME stolen Memory lock.
1 = Rank 2 populated
0 = Rank 2 not populated
This register is locked by ME stolen Memory lock.
21
RW/L
0b
Rank 1 Population (sd1_cr_rankpop1):
1 = Rank 1 populated
0 = Rank 1 not populated
This register is locked by ME stolen Memory lock.
1 = Rank 1 populated
0 = Rank 1 not populated
This register is locked by ME stolen Memory lock.
20
RW/L
0b
Rank 0 Population (sd1_cr_rankpop0):
1 = Rank 0 populated
0 = Rank 0 not populated
This register is locked by ME stolen Memory lock.
1 = Rank 0 populated
0 = Rank 0 not populated
This register is locked by ME stolen Memory lock.
19:17
RW
000b
CKE Pulse Width Requirement in Low Phase (sd1_cr_cke_pw_lh_safe):
This field indicates CKE pulse width requirement in low phase. This field
Corresponds to t
This field indicates CKE pulse width requirement in low phase. This field
Corresponds to t
CKE
(low) in the DDR Specification.
16
RW
0b
Enable CKE Toggle for PDN Entry/Exit (sd1_cr_pdn_enable): This bit
indicates that the toggling of CKEs (for PDN entry/exit) is enabled.
indicates that the toggling of CKEs (for PDN entry/exit) is enabled.
15:14
RO
00b
Reserved
13:10
RW
0010b
Minimum Powerdown Exit to Non-Read Command Spacing
(sd1_cr_txp): This field indicates the minimum number of clocks to wait
following assertion of CKE before issuing a non-read command.
1010–1111 = Reserved.
0010–1001 = 2–9 clocks
0000–0001 = Reserved.
(sd1_cr_txp): This field indicates the minimum number of clocks to wait
following assertion of CKE before issuing a non-read command.
1010–1111 = Reserved.
0010–1001 = 2–9 clocks
0000–0001 = Reserved.
9:1
RW
0000000
00b
Self Refresh Exit Count (sd1_cr_slfrfsh_exit_cnt): This configuration
register indicates the Self refresh exit count. (Program to 255)
Corresponds to t
register indicates the Self refresh exit count. (Program to 255)
Corresponds to t
XSNR
/t
XSRD
in the DDR Specification.
0
RW
0b
Indicates Only 1 DIMM Populated (sd1_cr_singledimmpop): This field
indicates the that only 1 DIMM is populated.
indicates the that only 1 DIMM is populated.