Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Ficha De Dados

288

Datasheet

NOTES:
1.

Determined with 2x MCH Buffer Strength Settings into a 50 Ω to 0.5xVCC_DDR test load. 

2.

Specified at the measurement point into a timing and voltage compliance test load as 
shown in Transmitter compliance eye diagram of PCI Express* specification and measured 
over any 250 consecutive TX Uls. 

3.

Specified at the measurement point over any 250 consecutive Uls. The test load shown in 
Receiver compliance eye diagram of PCI Express* spec should be used as the RX device 
when taking measurements.

4.

Applies to pin to VCC or VSS leakage current for the DDR_A_DQ_63:0 and 
DDR_B_DQ_63:0 signals.

5.

Applies to pin to pin leakage current between DDR_A_DQS_7:0, DDR_A_DQSB_7:0, 
DDR_B_DQS_7:0, and DDR_B_DQSB_7:0 signals.

6.

Crossing voltage defined as instantaneous voltage when rising edge of BCLK0 equals 
falling edge of BCLK1.

7.

V

Havg

 is the statistical average of the V

H

 measured by the oscilloscope.

8.

The crossing point must meet the absolute and relative crossing point specifications 
simultaneously. Refer to the appropriate processor datasheet for further information.

I

OH

Output High Current (CMOS 
Outputs)

-2.0

—

—

mA

@V

OH_HI

 

min

V

OL

Output Low Voltage (CMOS 
Outputs)

—

—

0.33

V

V

OH

Output High Voltage (CMOS 
Outputs)

2.97

—

 —

V

V

IL

Input Low Voltage

-0.10

0

(0.63 x VTT) – 

0.1

 

V

V

IH

Input High Voltage

(0.63 x 

VTT)+0.1

 

VTT

VTT +0.1

V

I

LEAK

Input Leakage Current

—

—

20

μA

V

OL

<

Vpad<
Vtt

C

IN

Input Capacitance

2

—

2.5

pF