Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Ficha De Dados
Códigos do produto
P4X-UPE3210-316-6M1333
DRAM Controller Registers (D0:F0)
90
Datasheet
5.1.33
TOLUD—Top of Low Usable DRAM
B/D/F/Type:
0/0/0/PCI
Address Offset: B0–B1h
Default Value:
0010h
Access:
RW/L, RO
Size:
16 bits
This 16 bit register defines the Top of Low Usable DRAM. TSEG, and Stolen Memory are
within the DRAM space defined. From the top, MCH optionally claims 1, 2 MB of DRAM
for Stolen Memory and 1, 2, or 8 MB of DRAM for TSEG if enabled.
Programming Example:
C1DRB3 is set to 4 GB
TSEG is enabled and TSEG size is set to 1 MB
Stolen Memory Size set to 2 MB
BIOS knows the OS requires 1 GB of PCI space.
BIOS also knows the range from FEC0_0000h to FFFF_FFFFh is not usable by the
system. This 20 MB range at the very top of addressable memory space is lost to APIC
and Intel TXT.
According to the above equation, TOLUD is originally calculated to: 4 GB =
1_0000_0000h
The system memory requirements are: 4GB (max addressable space) – 1GB (PCI
space) – 35 MB (lost memory) = 3 GB – 35 MB (minimum granularity) = ECB0_0000h
Since ECB0_0000h (PCI and other system requirements) is less than 1_0000_0000h,
TOLUD should be programmed to ECBh.
These bits are Intel TXT lockable.
Bit
Access
Default
Value
Description
15:4
RW/L
001h
Top of Low Usable DRAM (TOLUD): This register contains bits [31:20] of an
address one byte above the maximum DRAM memory below 4GB that is usable
by the operating system. Address bits [31:20] programmed to 01h implies a
minimum memory size of 1 MB. Configuration software must set this value to
the smaller of the following 2 choices: maximum amount memory in the system
minus ME stolen memory plus one byte or the minimum address allocated for
PCI memory. Address bits [19:0] are assumed to be 0_0000h for the purposes
of address comparison. The Host interface positively decodes an address
towards DRAM if the incoming address is less than the value programmed in this
register.
Note that the Top of Low Usable DRAM is the lowest address above both Stolen
memory and TSEG. BIOS determines the base of Stolen Memory by subtracting
the Stolen Memory Size from TOLUD and further decrements by TSEG size to
determine base of TSEG. All the Bits in this register are locked in Intel TXT
mode.
This register must be 64 MB aligned when reclaim is enabled.
address one byte above the maximum DRAM memory below 4GB that is usable
by the operating system. Address bits [31:20] programmed to 01h implies a
minimum memory size of 1 MB. Configuration software must set this value to
the smaller of the following 2 choices: maximum amount memory in the system
minus ME stolen memory plus one byte or the minimum address allocated for
PCI memory. Address bits [19:0] are assumed to be 0_0000h for the purposes
of address comparison. The Host interface positively decodes an address
towards DRAM if the incoming address is less than the value programmed in this
register.
Note that the Top of Low Usable DRAM is the lowest address above both Stolen
memory and TSEG. BIOS determines the base of Stolen Memory by subtracting
the Stolen Memory Size from TOLUD and further decrements by TSEG size to
determine base of TSEG. All the Bits in this register are locked in Intel TXT
mode.
This register must be 64 MB aligned when reclaim is enabled.
3:0
RO
0000b
Reserved