Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Ficha De Dados
Códigos do produto
P4X-UPE3210-316-6M1333
Datasheet
91
DRAM Controller Registers (D0:F0)
5.1.34
ERRSTS—Error Status
B/D/F/Type:
0/0/0/PCI
Address Offset: C8–C9h
Default Value:
0000h
Access:
RWC/S, RO
Size:
16 bits
This register is used to report various error conditions via the SERR DMI messaging
mechanism. An SERR DMI message is generated on a zero to one transition of any of
these flags (if enabled by the ERRCMD and PCICMD registers).
These bits are set regardless of whether or not the SERR is enabled and generated.
After the error processing is complete, the error logging mechanism can be unlocked by
clearing the appropriate status bit by software writing a 1 to it.
Bit
Access
Default
Value
Description
15
RO
0b
Reserved
14
RWC/S
0b
Isochronous TBWRR Run Behind FIFO Full (ITCV): If set, this bit indicates
a VC1 TBWRR is running behind, resulting in the slot timer to stop until the
request is able to complete.
If this bit is already set, then a interrupt message will not be sent on a new error
event.
a VC1 TBWRR is running behind, resulting in the slot timer to stop until the
request is able to complete.
If this bit is already set, then a interrupt message will not be sent on a new error
event.
13
RWC/S
0b
Isochronous TBWRR Run behind FIFO Put (ITSTV): If set, this bit indicates
a VC1 TBWRR request was put into the run behind. This will likely result in a
resulting in a contract violation due to the MCH egress port taking too long to
service the isochronous request.
If this bit is already set, then a interrupt message will not be sent on a new error
event.
a VC1 TBWRR request was put into the run behind. This will likely result in a
resulting in a contract violation due to the MCH egress port taking too long to
service the isochronous request.
If this bit is already set, then a interrupt message will not be sent on a new error
event.
12
RO
0b
Reserved
11
RWC/S
0b
MCH Thermal Sensor Event for SMI/SCI/SERR (GTSE): This bit indicates
that a MCH Thermal Sensor trip has occurred and an SMI, SCI or SERR has been
generated. The status bit is set only if a message is sent based on Thermal event
enables in Error command, SMI command and SCI command registers. A trip
point can generate one of SMI, SCI, or SERR interrupts (two or more per event is
illegal). Multiple trip points can generate the same interrupt, if software chooses
this mode, subsequent trips may be lost. If this bit is already set, then an
interrupt message will not be sent on a new thermal sensor event.
that a MCH Thermal Sensor trip has occurred and an SMI, SCI or SERR has been
generated. The status bit is set only if a message is sent based on Thermal event
enables in Error command, SMI command and SCI command registers. A trip
point can generate one of SMI, SCI, or SERR interrupts (two or more per event is
illegal). Multiple trip points can generate the same interrupt, if software chooses
this mode, subsequent trips may be lost. If this bit is already set, then an
interrupt message will not be sent on a new thermal sensor event.
10
RO
0b
Reserved
9
RWC/S
0b
LOCK to non-DRAM Memory Flag (LCKF): When this bit is set to 1, the MCH
has detected a lock operation to memory space that did not map into DRAM.
has detected a lock operation to memory space that did not map into DRAM.
8
RO
0b
Reserved
7
RWC/S
0b
DRAM Throttle Flag (DTF):
1 = Indicates that a DRAM Throttling condition occurred.
0 = Software has cleared this flag since the most recent throttling event.
1 = Indicates that a DRAM Throttling condition occurred.
0 = Software has cleared this flag since the most recent throttling event.
6:2
RO
00h
Reserved