Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Ficha De Dados

Datasheet

93

B/D/F/Type:

0/0/0/PCI

Address Offset: CA–CBh

Default Value:

0000h

Access:

RW, RO 

Size:

16 bits

This register controls the MCH responses to various system errors. Since the MCH does 

not have an SERRB signal, SERR messages are passed from the MCH to the ICH over 

DMI. 

When a bit in this register is set, a SERR message will be generated on DMI whenever 

the corresponding flag is set in the ERRSTS register. The actual generation of the SERR 

message is globally enabled for Device 0 via the PCI Command register.

15:12

RO

0h

Reserved

11

RW

0b

SERR on MCH Thermal Sensor Event (TSESERR): 
1 = The MCH generates a DMI SERR special cycle when bit [11] of the ERRSTS is 

set. The SERR must not be enabled at the same time as the SMI for the 
same thermal sensor event.

0 = Reporting of this condition via SERR messaging is disabled.

10

RO

0b

Reserved

9

RW

0b

SERR on LOCK to non-DRAM Memory (LCKERR): 
1 = The MCH will generate a DMI SERR special cycle whenever a processor lock 

cycle is detected that does not hit DRAM.

0 = Reporting of this condition via SERR messaging is disabled.

8:2

RO

0s

Reserved

1

RW

0b

SERR Multiple-Bit DRAM ECC Error (DMERR): 
1 = The MCH generates an SERR message over DMI when it detects a multiple-

bit error reported by the DRAM controller.

0 = Reporting of this condition via SERR messaging is disabled. 
For systems not supporting ECC this bit must be disabled.

0

RW

0b

SERR on Single-bit ECC Error (DSERR): 
1 = The MCH generates an SERR special cycle over DMI when the DRAM 

controller detects a single bit error.

0 = Reporting of this condition via SERR messaging is disabled.
For systems that do not support ECC this bit must be disabled.