Intel Xeon X3450 BX80605X3450 Manual Do Utilizador
Códigos do produto
BX80605X3450
Introduction
14
Intel® Xeon® Processor 3400 Series Datasheet, Volume 1
• Re-issues Configuration cycles that have been previously completed with the
Configuration Retry status.
• PCI Express reference clock is 100-MHz differential clock.
• Power Management Event (PME) functions.
• Dynamic lane numbering reversal as defined by the PCI Express Base Specification.
• Dynamic frequency change capability (2.5 GT/s - 5.0 GT/s)
• Dynamic width capability
• Message Signaled Interrupt (MSI and MSI-X) messages.
• Polarity inversion.
• Power Management Event (PME) functions.
• Dynamic lane numbering reversal as defined by the PCI Express Base Specification.
• Dynamic frequency change capability (2.5 GT/s - 5.0 GT/s)
• Dynamic width capability
• Message Signaled Interrupt (MSI and MSI-X) messages.
• Polarity inversion.
1.2.3
Direct Media Interface (DMI)
• Four lanes in each direction.
• 2.5 GT/s point-to-point DMI interface to PCH is supported.
• Raw bit-rate on the data pins of 2.5 GB/s, resulting in a real bandwidth per pair of
• 2.5 GT/s point-to-point DMI interface to PCH is supported.
• Raw bit-rate on the data pins of 2.5 GB/s, resulting in a real bandwidth per pair of
250 MB/s given the 8b/10b encoding used to transmit data across this interface.
Does not account for packet overhead and link maintenance.
Does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 1 GB/s in each direction
simultaneously, for an aggregate of 2 GB/s when DMI x4.
• Shares 100-MHz PCI Express reference clock.
• 64-bit downstream address format, but the processor never generates an address
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros).
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
• Supports the following traffic types to or from the PCH
— DMI -> PCI Express Port 0 write traffic
— DMI -> PCI Express Port 1 write traffic
— DMI -> DRAM
— DMI -> processor core
— DMI -> PCI Express Port 1 write traffic
— DMI -> DRAM
— DMI -> processor core
(Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only)
— Processor core -> DMI
• APIC and MSI interrupt messaging support
— Message Signaled Interrupt (MSI and MSI-X) messages
• Downstream SMI, SCI, and SERR error indication.
• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters.
• DC coupling – no capacitors between the processor and the PCH.
• Polarity inversion.
• PCH end-to-end lane reversal across the link.
• Supports Half Swing “low-power/low-voltage” and Full Swing “high-power/high-
• Polarity inversion.
• PCH end-to-end lane reversal across the link.
• Supports Half Swing “low-power/low-voltage” and Full Swing “high-power/high-
voltage” modes.
1.2.4
Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between
processor and a PECI master, usually the PCH.
processor and a PECI master, usually the PCH.