Manuais de utilizador para Intel Xeon X3450

índice analítico

• Intel® Xeon® Processor 3400 Series

  1
• 1 Introduction

  9
  • 1.1 Processor Feature Details

    11
    • 1.1.1 Supported Technologies

      11
  • 1.2 Interfaces

    12
    • 1.2.1 System Memory Support

      12
    • 1.2.2 PCI Express*

      13
    • 1.2.3 Direct Media Interface (DMI)

      14
    • 1.2.4 Platform Environment Control Interface (PECI)

      14
  • 1.3 Power Management Support

    15
    • 1.3.1 Processor Core

      15
    • 1.3.2 System

      15
    • 1.3.3 Memory Controller

      15
    • 1.3.4 PCI Express*

      15
  • 1.4 Thermal Management Support

    15
  • 1.5 Package

    15
  • 1.6 Terminology

    16
  • 1.7 Related Documents

    18
• 2 Interfaces

  19
  • 2.1 System Memory Interface

    19
    • 2.1.1 System Memory Technology Supported

      19
    • 2.1.2 System Memory Timing Support

      20
    • 2.1.3 System Memory Organization Modes

      20
    • 2.1.4 Rules for Populating Memory Slots

      22
    • 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)

      23
    • 2.1.6 System Memory Pre-Charge Power Down Support Details

      23
  • 2.2 PCI Express* Interface

    24
    • 2.2.1 PCI Express* Architecture

      24
    • 2.2.2 PCI Express* Configuration Mechanism

      26
    • 2.2.3 PCI Express* Ports and Bifurcation

      26
  • 2.3 Direct Media Interface (DMI)

    27
    • 2.3.1 DMI Error Flow

      27
    • 2.3.2 Processor/PCH Compatibility Assumptions

      27
    • 2.3.3 DMI Link Down

      27
  • 2.4 Platform Environment Control Interface (PECI)

    28
  • 2.5 Interface Clocking

    28
    • 2.5.1 Internal Clocking Requirements

      28
• 3 Technologies

  29
  • 3.1 Intel® Virtualization Technology

    29
    • 3.1.1 Intel® VT-x Objectives

      29
    • 3.1.2 Intel® VT-x Features

      29
    • 3.1.3 Intel® VT-d Objectives

      30
    • 3.1.4 Intel® VT-d Features

      30
    • 3.1.5 Intel® VT-d Features Not Supported

      31
  • 3.2 Intel® Trusted Execution Technology (Intel® TXT)

    31
  • 3.3 Intel® Hyper-Threading Technology

    32
  • 3.4 Intel® Turbo Boost Technology

    32
• 4 Power Management

  33
  • 4.1 ACPI States Supported

    33
    • 4.1.1 System States

      33
    • 4.1.2 Processor Core/Package Idle States

      33
    • 4.1.3 Integrated Memory Controller States

      33
    • 4.1.4 PCI Express* Link States

      34
    • 4.1.5 Interface State Combinations

      34
  • 4.2 Processor Core Power Management

    34
    • 4.2.1 Enhanced Intel® SpeedStep® Technology

      35
    • 4.2.2 Low-Power Idle States

      35
    • 4.2.3 Requesting Low-Power Idle States

      37
    • 4.2.4 Core C-states

      37
    • 4.2.5 Package C-States

      39
  • 4.3 IMC Power Management

    41
    • 4.3.1 Disabling Unused System Memory Outputs

      41
    • 4.3.2 DRAM Power Management and Initialization

      42
  • 4.4 PCI Express* Power Management

    43
• 5 Thermal Management

  45
• 6 Signal Description

  47
  • 6.1 System Memory Interface

    48
  • 6.2 Memory Reference and Compensation

    50
  • 6.3 Reset and Miscellaneous Signals

    50
  • 6.4 PCI Express* Based Interface Signals

    51
  • 6.5 DMI — Processor to PCH Serial Interface

    52
  • 6.6 PLL Signals

    52
  • 6.7 Intel® Flexible Display Interface Signals

    52
  • 6.8 JTAG/ITP Signals

    53
  • 6.9 Error and Thermal Protection

    54
  • 6.10 Power Sequencing

    55
  • 6.11 Processor Core Power Signals

    55
  • 6.12 Graphics and Memory Core Power Signals

    57
  • 6.13 Ground and NCTF

    58
  • 6.14 Processor Internal Pull Up/Pull Down

    58
• 7 Electrical Specifications

  59
  • 7.1 Power and Ground Lands

    59
  • 7.2 Decoupling Guidelines

    59
    • 7.2.1 Voltage Rail Decoupling

      59
  • 7.3 Processor Clocking (BCLK[0], BCLK#[0])

    60
    • 7.3.1 PLL Power Supply

      60
  • 7.4 VCC Voltage Identification (VID)

    60
  • 7.5 Reserved or Unused Signals

    64
  • 7.6 Signal Groups

    64
  • 7.7 Test Access Port (TAP) Connection

    67
  • 7.8 Absolute Maximum and Minimum Ratings

    67
  • 7.9 DC Specifications

    68
    • 7.9.1 Voltage and Current Specifications

      68
  • 7.10 Platform Environmental Control Interface (PECI) DC Specifications

    74
    • 7.10.1 DC Characteristics

      75
    • 7.10.2 Input Device Hysteresis

      75
• 8 Processor Land and Signal Information

  77
  • 8.1 Processor Land Assignments

    77