Intel Xeon X3450 BX80605X3450 Manual Do Utilizador

52

Intel® Xeon® Processor 3400 Series Datasheet, Volume 1

The signals noted below as not being used are included for reference to define all LGA 

1156 land locations. These signals will be used by future processors that are 

compatible with LGA 1156 platforms. 

DMI_RX[3:0]

DMI_RX#[3:0]

DMI input from PCH: Direct Media Interface receive 

differential pair.

I

DMI

DMI_TX[3:0]

DMI_TX#[3:0]

DMI output to PCH: Direct Media Interface transmit 

differential pair.

O

DMI

BCLK[0]

BCLK#[0]

Differential bus clock input to the processor.

I

Diff Clk

BCLK[1]

BCLK#[1]

Differential bus clock input to the processor. Reserved 

for possible future use.

I

Diff Clk

BCLK_ITP

BCLK_ITP#

Buffered differential bus clock pair to ITP.

O

Diff Clk

PEG_CLK

PEG_CLK#

Differential PCI Express / DMI Clock In:
These pins receive a 100-MHz Serial Reference clock. 

This clock is used to generate the clocks necessary for 

the support of PCI Express. This also is the reference 

clock for Intel

®

 Flexible Display Interface. 

I

Diff Clk

FDI_FSYNC[0]

Intel

®

 Flexible Display Interface Frame Sync - Pipe A.

Note: This signal is not used by the processor. It is 

connected to V

SS

 on the package.

FDI_FSYNC[1]

Intel

®

 Flexible Display Interface Frame Sync - Pipe B.

Note: This signal is not used by the processor. It is 

connected to V

SS

 on the package.

FDI_INT

Intel

®

 Flexible Display Interface Hot Plug Interrupt.

Note: This signal is not used by the processor. It is 

connected to V

SS

 on the package.

FDI_LSYNC[0]

Intel

®

 Flexible Display Interface Line Sync - Pipe A.

Note: This signal is not used by the processor. It is 

connected to V

SS

 on the package.