Intel D525 AU80610006225AA Manual Do Utilizador
Códigos do produto
AU80610006225AA
Signal Description
16
Datasheet
2.1
CPU Legacy Signal
Table 2-4. CPU Legacy Signal
Signal Name
Description
Direction
Type
A20M#
If A20M# (Address-20 Mask) is asserted, the
processor masks physical address bit 20 (A20#)
before looking up a line in any internal cache and
before driving a read/write transaction on the bus.
Asserting A20M# emulates the 8086 processor's
address wrap-around at the 1-MB boundary.
Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to
ensure recognition of this signal following an input/
output write instruction, it must be valid along with
the TRDY# assertion of the corresponding input/
output Write bus transaction.
processor masks physical address bit 20 (A20#)
before looking up a line in any internal cache and
before driving a read/write transaction on the bus.
Asserting A20M# emulates the 8086 processor's
address wrap-around at the 1-MB boundary.
Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to
ensure recognition of this signal following an input/
output write instruction, it must be valid along with
the TRDY# assertion of the corresponding input/
output Write bus transaction.
I
Core
CMOS
BSEL[2:0]
BSEL[2:0] (Bus Select) are used to select the
processor input clock frequency.
processor input clock frequency.
O
Core
CMOS
EXTBGREF
External Bandgap Reference. Debug feature.
I
Core
Analog
FERR#/PBE#
FERR# (Floating-point Error)/PBE# (Pending Break
Event) is a multiplexed signal and its meaning is
qualified with STPCLK#. When STPCLK# is not
asserted, FERR#/PBE# indicates a floating point
when the processor detects an unmasked floating-
point error. FERR# is similar to the ERROR# signal
on the Intel 387 coprocessor, and is included for
compatibility with systems using MSDOS*- type
floating-point error reporting. When STPCLK# is
asserted, an assertion of FERR#/PBE# indicates that
the processor has a pending break event waiting for
service. The assertion of FERR#/PBE# indicates that
the processor should be returned to the Normal
state. When FERR#/PBE# is asserted, indicating a
break event, it will remain asserted until STPCLK# is
deasserted. Assertion of PREQ# when STPCLK# is
active will also cause an FERR# break event.
For additional information on the pending break
event functionality, including identification of
support of the feature and enable/disable
information, refer to Volume 3 of the
Event) is a multiplexed signal and its meaning is
qualified with STPCLK#. When STPCLK# is not
asserted, FERR#/PBE# indicates a floating point
when the processor detects an unmasked floating-
point error. FERR# is similar to the ERROR# signal
on the Intel 387 coprocessor, and is included for
compatibility with systems using MSDOS*- type
floating-point error reporting. When STPCLK# is
asserted, an assertion of FERR#/PBE# indicates that
the processor has a pending break event waiting for
service. The assertion of FERR#/PBE# indicates that
the processor should be returned to the Normal
state. When FERR#/PBE# is asserted, indicating a
break event, it will remain asserted until STPCLK# is
deasserted. Assertion of PREQ# when STPCLK# is
active will also cause an FERR# break event.
For additional information on the pending break
event functionality, including identification of
support of the feature and enable/disable
information, refer to Volume 3 of the
Intel®
64 and
IA-32 Architectures Software Developer's Manuals
and the
and the
Intel®
Processor Identification and CPUID
Instruction Application Note. For
termination requirements, refer to the platform
design guide.
termination requirements, refer to the platform
design guide.
O
Core
Open
Drain
Drain