Intel D525 AU80610006225AA Manual Do Utilizador
Códigos do produto
AU80610006225AA
Signal Description
20
Datasheet
Table 2-6. Memory Reference and Compensation
NOTE: Please refer to appropriate platform design guide for connections recommendations.
Table 2-7. Reset and Miscellaneous Signal
NOTE: RSVD_* numbering needs to be observed for BSDL testing purposes.
Signal
Name
Description Direction
Type
DDR_RPD
System Memory RCOMP signal. Refer Platform Design for
connection recommendation.
connection recommendation.
I/O
Analog
DDR_RPU
System Memory RCOMP signal. Refer Platform Design for
connection recommendation.
connection recommendation.
I/O
Analog
DDR_VREF
SDRAM Reference Voltage: external reference voltage
input for each DQ, DQS. Internal VREF is also supported.
input for each DQ, DQS. Internal VREF is also supported.
I
Analog
DDR_PREF
Reserved.
O
N/A
Signal Name
Description Direction
Type
RSTINB
Reset In: When asserted, this signal will asynchronously reset
the CPU logic. The signal is connected to the PCIRST# output
of the Intel NM10 Express Chipset.
This input should have a Schmitt trigger to avoid spurious
resets.
This signal is required to be 3.3-V tolerant.
the CPU logic. The signal is connected to the PCIRST# output
of the Intel NM10 Express Chipset.
This input should have a Schmitt trigger to avoid spurious
resets.
This signal is required to be 3.3-V tolerant.
I
HVCMOS
PWROK
Power OK: When asserted, PWROK is an indication to the CPU
that core power has been stable for at least 10us.
This input should have a Schmitt trigger to avoid spurious
resets. This signal is required to be 3.3V tolerant.
that core power has been stable for at least 10us.
This input should have a Schmitt trigger to avoid spurious
resets. This signal is required to be 3.3V tolerant.
I
HVCMOS
DDR3_DRAM_PWROK
DDR3 power good monitor. Driven by platform logic for DDR3.
Reserved for DDR2 designs
Reserved for DDR2 designs
I
CMOS-
1.5
DDR3_DRAMRST#
DDR3 DRAM reset. Reset signal from IMC to DRAM devices.
One for all SO-DIMMs. Used only in DDR3 mode. Reserved for
DDR2 designs.
One for all SO-DIMMs. Used only in DDR3 mode. Reserved for
DDR2 designs.
O
SSTL-1.5
RSVD_*
Reserved. Must be left unconnected on the board. Intel does
not recommend a test point on the board for this ball.
not recommend a test point on the board for this ball.
NC
RSVD_NCTF_*
Reserved/non-critical to function. Pin for package mechanical
reliability. A test point may be placed on the board for this
ball.
reliability. A test point may be placed on the board for this
ball.
I/O
RSVD_TP_*
Reserved-test-point. A test point may be placed on the board
for this ball.
for this ball.
I/O
XDP_RSVD_[17:0]
Reserved XDP debug signals.