Intel 220 LE80557RE009512 Ficha De Dados

Datasheet

15

When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered 

20 bus clocks after the response phase of the processor-issued Stop Grant 

Acknowledge special bus cycle.

Since the GTL+ signals receive power from the FSB, these signals should not be driven 

(allowing the level to return to 

V

CCP

) for minimum power drawn by the termination 

resistors in this state. In addition, all other input signals on the FSB should be driven to 

the inactive state.

RESET# will cause the processor to immediately initialize itself, but the processor will 

stay in Stop-Grant state. A transition back to the Normal state will occur with the de-

assertion of the STPCLK# signal.

A transition to the Grant Snoop state will occur when the processor detects a snoop on 

the FSB (see 

).

While in the Stop-Grant State, SMI#, INIT#, and LINT[1:0] will be latched by the 

processor, and only serviced when the processor returns to the Normal State. Only one 

occurrence of each event will be recognized upon return to the Normal state.

While in Stop-Grant state, the processor will process a FSB snoop. 

The processor will respond to snoop transactions on the FSB while in Stop-Grant state 

or in HALT Power Down state. During a snoop transaction, the processor enters the 

HALT Snoop State:Stop Grant Snoop state. The processor will stay in this state until the 

snoop on the FSB has been serviced (whether by the processor or another agent on the 

FSB). After the snoop is serviced, the processor will return to the Stop Grant state or 

HALT Power Down state, as appropriate.