Intel 220 LE80557RE009512 Ficha De Dados

Códigos do produto
LE80557RE009512
Página de 66
Electrical Specifications
22
Datasheet
3.4
Catastrophic Thermal Protection
The Celeron processor supports the THERMTRIP# signal for catastrophic thermal 
protection. An external thermal sensor should also be used to protect the processor 
and the system against excessive temperatures. Even with the activation of 
THERMTRIP#, which halts all processor internal clocks and activity, leakage current can 
be high enough such that the processor cannot be protected in all conditions without 
the removal of power to the processor. If the external thermal sensor detects a 
catastrophic processor temperature of 125 °C (maximum), or if the THERMTRIP# 
signal is asserted, the V
CC
 supply to the processor must be turned off within 500 ms to 
prevent permanent silicon damage due to thermal runaway of the processor. 
THERMTRIP# functionality is not ensured if the PWRGOOD signal is not asserted.
3.5
Reserved and Unused Pins
All RESERVED (RSVD) pins must remain unconnected. Connection of these pins to V
CC
V
SS
, or to any other signal (including each other) can result in component malfunction 
or incompatibility with future Celeron processors. See 
 for a pin listing of the 
processor and the location of all RSVD pins.
For reliable operation, always connect unused inputs or bidirectional signals to an 
appropriate signal level. Unused active low GTL+ inputs may be left as no connects if 
GTL+ termination is provided on the processor silicon. Unused active high inputs should 
be connected through a resistor to ground (V
SS
). Unused outputs can be left 
unconnected. 
The TEST1 and TEST2 pins must have a stuffing option of separate pulldown resistors 
to V
SS
. For testing purposes, route the TEST3 and TEST5 signals through a ground 
referenced Z
= 55-Ω trace that ends in a via that is near a GND via and is accessible 
through an oscilloscope connection.
3.6
FSB Frequency Select Signals (BSEL[2:0]) 
The BSEL[2:0] signals are used to select the frequency of the processor input clock 
(BCLK[1:0]). These signals should be connected to the clock chip and the chipset 
system on the platform. The BSEL encoding for BCLK[1:0] is shown in 
Table 3.
BSEL[2:0] Encoding for BCLK Frequency
BSEL[2]
BSEL[1]
BSEL[0]
BCLK Frequency
L
L
L
RESERVED
L
L
H
133 MHz