IBM powerpc 750gx Manual Do Utilizador
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Memory Management
Page 192 of 377
gx_05.fm.(1.2)
March 27, 2006
If the T bit in the Segment Register is cleared (SR[T] = 0), then page-address translation is selected. The
information in the segment descriptor is then used to generate the 52-bit virtual address. The virtual address
is used to identify the page-address-translation information (stored as page table entries [PTEs] in a page
table in memory). For increased performance, the 750GX has two on-chip TLBs to cache recently-used trans-
lations on-chip.
information in the segment descriptor is then used to generate the 52-bit virtual address. The virtual address
is used to identify the page-address-translation information (stored as page table entries [PTEs] in a page
table in memory). For increased performance, the 750GX has two on-chip TLBs to cache recently-used trans-
lations on-chip.
If an access hits in the appropriate TLB, page translation succeeds and the physical address bits are
forwarded to the memory subsystem. If the required translation is not resident, the MMU performs a search of
the page table. If the required PTE is found, a TLB entry is allocated and the page translation is attempted
again. This time, the TLB is guaranteed to hit. When the translation is located, the access is qualified with the
appropriate protection bits. If the access causes a protection violation, either an ISI or DSI exception is gener-
ated.
forwarded to the memory subsystem. If the required translation is not resident, the MMU performs a search of
the page table. If the required PTE is found, a TLB entry is allocated and the page translation is attempted
again. This time, the TLB is guaranteed to hit. When the translation is located, the access is qualified with the
appropriate protection bits. If the access causes a protection violation, either an ISI or DSI exception is gener-
ated.
If the PTE is not found by the table-search operation, a page-fault condition exists, and an ISI or DSI excep-
tion occurs so software can handle the page fault.
tion occurs so software can handle the page fault.
5.1.7 MMU Exceptions Summary
To complete any memory access, the effective address must be translated to a physical address. As speci-
fied by the architecture, an MMU exception condition occurs if this translation fails for one of the following
reasons:
fied by the architecture, an MMU exception condition occurs if this translation fails for one of the following
reasons:
• Page fault. There is no valid entry in the page table for the page specified by the effective address (and
segment descriptor), and there is no valid BAT translation.
• An address translation is found, but the access is not allowed by the memory-protection mechanism.
The translation exception conditions defined by the OEA for 32-bit implementations cause either the ISI or the
DSI exception to be taken as shown in Table 5-3.
DSI exception to be taken as shown in Table 5-3.
I
Table 5-3. Translation Exception Conditions
(Page 1 of 2)
Condition Description
Exception
Page fault (no PTE found)
No matching PTE found in page tables (and no matching
BAT array entry)
BAT array entry)
I access: ISI exception
SRR1[1] = 1
D access: DSI exception
DSISR[1] =1
Block protection violation
Conditions described for blocks in “Block Memory Pro-
tection” in Chapter 7, “Memory Management,” in the
PowerPC Microprocessor Family: The Programming
Environments Manual.“
tection” in Chapter 7, “Memory Management,” in the
PowerPC Microprocessor Family: The Programming
Environments Manual.“
I access: ISI exception
SRR1[4] = 1
D access: DSI exception
DSISR[4] =1
Page-protection violation
Conditions described for pages in “Page Memory Protec-
tion” in Chapter 7, “Memory Management,” in the Pow-
erPC Microprocessor Family: The Programming
Environments Manual.
tion” in Chapter 7, “Memory Management,” in the Pow-
erPC Microprocessor Family: The Programming
Environments Manual.
I access: ISI exception
SRR1[4] = 1
D access: DSI exception
DSISR[4] = 1
No-execute protection violation
Attempt to fetch instruction when SR[N] = 1
ISI exception
SRR1[3] = 1