IBM powerpc 750gx Manual Do Utilizador
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Signal Descriptions
Page 268 of 377
gx_07.fm.(1.2)
March 27, 2006
Data-Bus Parity (DP[0–7])—Input
7.2.7.3 Data Bus Disable (DBDIS)—Input
7.2.8 Data-Transfer Termination Signals
Data termination signals are required after each data beat in a data transfer. Note that in a single-beat trans-
action, the data termination signals also indicate the end of the tenure, while in burst accesses, the data
termination signals apply to individual beats and indicate the end of the tenure only after the final data beat.
action, the data termination signals also indicate the end of the tenure, while in burst accesses, the data
termination signals apply to individual beats and indicate the end of the tenure only after the final data beat.
For a detailed description of how these signals interact, see Section 8.4.4, Data-Transfer Termination, on
page 303.
page 303.
7.2.8.1 Transfer Acknowledge (TA)—Input
State
Asserted/
Negated
Negated
Represents odd parity for each byte of read data. Parity is checked on all
data byte lanes, regardless of the size of the transfer. Detected even parity
causes a checkstop if data-parity errors are enabled in the HID0 register.
data byte lanes, regardless of the size of the transfer. Detected even parity
causes a checkstop if data-parity errors are enabled in the HID0 register.
Timing
Assertion/
Negation
Negation
The same as DL[0–31].
State
Asserted
Indicates (for a write transaction) that the 750GX must release the data bus
and data-bus parity to high impedance during the following cycle. The data
tenure will remain active, DBB will remain driven, and the transfer termina-
tion signals will still be monitored by the 750GX.
and data-bus parity to high impedance during the following cycle. The data
tenure will remain active, DBB will remain driven, and the transfer termina-
tion signals will still be monitored by the 750GX.
Negated
Indicates the data bus should remain driven if it otherwise would have been.
DBDIS is ignored during read transactions.
DBDIS is ignored during read transactions.
Timing
Assertion/
Negation
Negation
May be asserted on any clock; will not otherwise affect the operation of the
bus if the 750GX is not running a bus transaction or if the 750GX is running a
read transaction.
bus if the 750GX is not running a bus transaction or if the 750GX is running a
read transaction.
Start-Up
See Table 7-6, Summary of Mode Select Signals, on page 274 for a descrip-
tion of the start-up function.
tion of the start-up function.
State
Asserted
Indicates that data on the data bus has been provided or accepted by the
system. On the following cycle, the 750GX will terminate the data beat
(unless DRTRY extends a read data beat), and if a burst, advance to the
next data beat. If it is the last or only data beat, the 750GX will also terminate
the data tenure (unless DRTRY extends a read data beat). TA must always
be asserted on the same cycle as valid data on the data bus, even if during
the final assertion cycle of DRTRY for that beat.
system. On the following cycle, the 750GX will terminate the data beat
(unless DRTRY extends a read data beat), and if a burst, advance to the
next data beat. If it is the last or only data beat, the 750GX will also terminate
the data tenure (unless DRTRY extends a read data beat). TA must always
be asserted on the same cycle as valid data on the data bus, even if during
the final assertion cycle of DRTRY for that beat.
Negated
Indicates that the 750GX must extend the current data beat (by inserting
wait states) until data can be provided or accepted by the system. TA might
also be negated anytime during a DRTRY assertion except on the last cycle
of the DRTRY assertion.
wait states) until data can be provided or accepted by the system. TA might
also be negated anytime during a DRTRY assertion except on the last cycle
of the DRTRY assertion.