IBM powerpc 750gx Manual Do Utilizador
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_07.fm.(1.2)
March 27, 2006
March 27, 2006
Signal Descriptions
Page 269 of 377
7.2.8.2 Data Retry (DRTRY)—Input
7.2.8.3 Transfer Error Acknowledge (TEA)—Input
Timing
Assertion
Might occur on any cycle during the normal or extended data-bus tenure for
the 750GX (see DBB and DRTRY). Must not occur two cycles or more
before ARTRY assertion if ARTRY cancellation is to be used.
the 750GX (see DBB and DRTRY). Must not occur two cycles or more
before ARTRY assertion if ARTRY cancellation is to be used.
Negation
For a burst, must occur the cycle after the assertion of TA unless another
assertion of TA is immediately required for the next data beat.
assertion of TA is immediately required for the next data beat.
Note: It is the responsibility of the system to ensure that TA is negated by the start of the
next data-bus tenure.
next data-bus tenure.
Warning: If configured for 1x clock mode and performing a data (not instruction) burst read,
the 750GX requires one wait state between the assertion of TS and the first assertion of TA.
If No-DRTRY mode is also selected, the 750GX requires two wait states for 1x clock mode,
or one wait state for 1.5x clock mode.
the 750GX requires one wait state between the assertion of TS and the first assertion of TA.
If No-DRTRY mode is also selected, the 750GX requires two wait states for 1x clock mode,
or one wait state for 1.5x clock mode.
State
Asserted
During a read transaction, indicates that the 750GX must cancel data
received on the previous cycle with a valid TA, and extend that data beat
until new valid data with a new TA is provided. While asserted, DRTRY also
extends the data-bus tenure of the current transaction if the last or only data
beat was retried and DBB has already negated.
received on the previous cycle with a valid TA, and extend that data beat
until new valid data with a new TA is provided. While asserted, DRTRY also
extends the data-bus tenure of the current transaction if the last or only data
beat was retried and DBB has already negated.
Negated
Indicates that read data presented with TA on the previous bus cycle is valid.
DRTRY is ignored as a data termination control during write transactions.
Timing
Assertion
Must occur the cycle following the assertion of TA, if a data retry is required.
Once asserted must remain asserted until a valid TA and data are provided.
Once asserted must remain asserted until a valid TA and data are provided.
Negation
Must occur the cycle following the presentation of valid data and a TA to the
750GX. This might occur several cycles after the negation of DBB.
750GX. This might occur several cycles after the negation of DBB.
Start-Up
Sampled at the negation of the hard reset (HRESET) signal to select
DRTRY-enabled mode if negated, or No-DRTRY mode if asserted. See
Table 7-6, Summary of Mode Select Signals, on page 274 for a description
of the start-up function.
DRTRY-enabled mode if negated, or No-DRTRY mode if asserted. See
Table 7-6, Summary of Mode Select Signals, on page 274 for a description
of the start-up function.
State
Asserted
Indicates that a data-bus error has occurred. On the following cycle, the
750GX must terminate the data tenure. Internally, the 750GX will also take a
machine-check interrupt or enter the checkstop state (see Chapter 10,
Power and Thermal Management, on page 335). For reads, a TEA will not
invalidate data entering the General Purpose Registers (GPRs) or the
caches.
750GX must terminate the data tenure. Internally, the 750GX will also take a
machine-check interrupt or enter the checkstop state (see Chapter 10,
Power and Thermal Management, on page 335). For reads, a TEA will not
invalidate data entering the General Purpose Registers (GPRs) or the
caches.
Negated
Indicates that no bus error was detected.