Axiom Manufacturing Inc 0511AXM0361 Manual Do Utilizador

5

J2 is an alternate application interface connector provided for applications on the
MC68EVB9S08GB60 development board GP Port connector or to replace the
MC13192RFC module in application. This connector is not installed or applied in the
standard kit, contact the factory for a module version to apply this connector.

 Signal Name

ANTCTL

1

2

x

IDLE (GPIO1)

3

4

V_CRC (GPIO2)

x

5

6

x

x

7

8

x

IRQ_OUT*

9

10

x

x

11

12

x

x

13

14

CLOCK  OUT  (JP2)

x

15

16

x

x

17

18

x

x

19

20

x

RXTXEN

21

22

RESET_IN*

x

23

24

ATTN_IN*

SIN

25

26

SCK

SEL*

27

28

SOUT

VDD (3.3)

29

30

GND (vss)

Notes:
1)  Signal names refer to the MC13192U operation.

2) 

The ‘*’ symbol indicates low active signal.

3) 

J2 will align with the bottom half or GP Port pins 11 – 40 on the MC68EVB9S08GB60 board.

J104 is provided for factory testing and verification.  It is possible for the user to modify
the MC13192U module to apply this connection for testing purposes or to apply an
external antenna.

Any modification to the module or application of an external antenna is
prohibited. Any change to the module from factory standard will render the
provided FCC registration void and possibly all other provided agency
certifications void. The user must assume full responsibility for module operation
and pursue the proper regulatory testing and agency registrations in this case!    

The module applies the J1 connector, a 24 pin (2x12) right angle .1 inch space pin
header, for connection to the host controlling platform by default. This connector is
configured for compatibility with many Freescale DEMO series MCU boards or Axiom
CSM series microcontroller application boards, and the MCUSLK Project Board. User
should review the Supporting Platform section for standard connections to host
controller platforms.