Murata Electronics North America XDM2140 Manual Do Utilizador
Mode 1 Pin Usage
Pin
I/O
Usage
RX
Input
Serial data moving from the microcontroller to the XDM2140.
TX
Output
Serial data moving from the XDM2140 to the microcontroller.
/MT_RTS
Output
/MT_RTS provides a mechanism to wake up the microcontroller in order to receive a packet. This signal
is asserted when the XDM2140 is ready to send a serial packet. The signal stays low until the /SP_CTS
signal from the microcontroller is detected low by the XDM2140 (indicating readiness to receive a
packet) or the timeout defined in Section 8.4.3 expires. /MT_RTS may be ignored by the microcontroller
only if /SP_CTS always stays low.
is asserted when the XDM2140 is ready to send a serial packet. The signal stays low until the /SP_CTS
signal from the microcontroller is detected low by the XDM2140 (indicating readiness to receive a
packet) or the timeout defined in Section 8.4.3 expires. /MT_RTS may be ignored by the microcontroller
only if /SP_CTS always stays low.
/SP_CTS
Input
/SP_CTS provides packet level flow control for packets transferred from the XDM2140 to the
microcontroller. When the microcontroller is capable of receiving a packet it should assert the /SP_CTS
signal. /SP_CTS may be externally tied low (reducing pin count) only if the microcontroller is always
ready to receive a serial packet.
microcontroller. When the microcontroller is capable of receiving a packet it should assert the /SP_CTS
signal. /SP_CTS may be externally tied low (reducing pin count) only if the microcontroller is always
ready to receive a serial packet.
/MT_CTS
Output
/MT_CTS provides packet level flow control for packets transferred from the microcontroller to the
XDM2140 that are destined for transfer over the network. Upon reset, following boot the XDM2140 will
negate /MT_CTS until the XDM2140 establishes a wireless network connection. During operation, the
XDM2140 will negate /MT_CTS if the XDM2140 does not have sufficient buffering to accept another
packet. /MT_CST will also remain high if the XDM2140 is not part of the network. The microcontroller
must check that the /MT_CTS pin is low before initiating each serial packet for wireless transmission.
Note that the XDM2140 may receive local serial packets at any time regardless of the /MT_CTS state.
XDM2140 that are destined for transfer over the network. Upon reset, following boot the XDM2140 will
negate /MT_CTS until the XDM2140 establishes a wireless network connection. During operation, the
XDM2140 will negate /MT_CTS if the XDM2140 does not have sufficient buffering to accept another
packet. /MT_CST will also remain high if the XDM2140 is not part of the network. The microcontroller
must check that the /MT_CTS pin is low before initiating each serial packet for wireless transmission.
Note that the XDM2140 may receive local serial packets at any time regardless of the /MT_CTS state.
/TIME
Input
The /TIME pin can be used for triggering a timestamp packet. Its usage is optional.
Table 14
8.4.2 Mode 3 - Five-signal Serial Interface (9600 b/s
)
XDM2140 Mode 3 provides a five-signal serial interface with byte-level flow control on transfers from the
XDM2140 to the microcontroller. The Mode 3 serial interface is comprised of the data pins UART_TX
and UART_RX, with handshake pins /MT_RTS, /MT_CTS and /SP_CTS used for bidirectional flow
control. The /MT_RTS signal is ideal for designs where the microcontroller requires extra time to prepare
to receive a packet. For example, the host microcontroller sleeps periodically and requires a wake-up
signal prior to receiving a packet). Refer to Table 15 for information on each handshake pin, including
details on which of those pins are optional.
XDM2140 to the microcontroller. The Mode 3 serial interface is comprised of the data pins UART_TX
and UART_RX, with handshake pins /MT_RTS, /MT_CTS and /SP_CTS used for bidirectional flow
control. The /MT_RTS signal is ideal for designs where the microcontroller requires extra time to prepare
to receive a packet. For example, the host microcontroller sleeps periodically and requires a wake-up
signal prior to receiving a packet). Refer to Table 15 for information on each handshake pin, including
details on which of those pins are optional.
Mode 3 Pin Usage
Pin
I/O
Usage
RX
Input
Serial data moving from the microcontroller to the XDM2140.
TX
Output
Serial data moving from the XDM2140 to the microcontroller.
/MT_RTS
Output
/MT_RTS provides a mechanism to wake up the microcontroller in order to receive a packet. This signal
is asserted when the XDM2140 is ready to send a serial packet. The signal stays low until the /SP_CTS
signal from the microcontroller is detected low by the XDM2140 (indicating readiness to receive a
packet) or the t
is asserted when the XDM2140 is ready to send a serial packet. The signal stays low until the /SP_CTS
signal from the microcontroller is detected low by the XDM2140 (indicating readiness to receive a
packet) or the t
ack_delay
timeout defined in Section 8.4.3 expires.
/SP_CTS
Input
/SP_CTS provides both packet and byte level flow control for packets transferred from the XDM2140 to
the microcontroller. When the microcontroller is capable of receiving a packet it should assert the
/SP_CTS signal. In Mode 3, byte-level flow control is achieved by having the microcontroller negate and
then reassert the /SP_CTS signal following the receipt of each byte. The XDM2140 will begin
transmission of the next byte after detecting the reassertion of /SP_CTS.
the microcontroller. When the microcontroller is capable of receiving a packet it should assert the
/SP_CTS signal. In Mode 3, byte-level flow control is achieved by having the microcontroller negate and
then reassert the /SP_CTS signal following the receipt of each byte. The XDM2140 will begin
transmission of the next byte after detecting the reassertion of /SP_CTS.
/MT_CTS
Output
/MT_CTS provides packet level flow control for packets transferred from the microcontroller to the
XDM2140 that are destined for transfer over the network. Upon reset, following boot the XDM2140 will
negate /MT_CTS until the XDM2140 establishes a wireless network connection. During operation, the
XDM2140 will negate /MT_CTS if the XDM2140 does not have sufficient buffering to accept another
packet. /MT_CTS will also remain high if the XDM2140 is not part of the network. The microcontroller
must check that the /MT_CTS pin is low before initiating each serial packet for wireless transmission.
Note that the XDM2140 may receive local serial packets at any time regardless of the /MT_CTS state.
XDM2140 that are destined for transfer over the network. Upon reset, following boot the XDM2140 will
negate /MT_CTS until the XDM2140 establishes a wireless network connection. During operation, the
XDM2140 will negate /MT_CTS if the XDM2140 does not have sufficient buffering to accept another
packet. /MT_CTS will also remain high if the XDM2140 is not part of the network. The microcontroller
must check that the /MT_CTS pin is low before initiating each serial packet for wireless transmission.
Note that the XDM2140 may receive local serial packets at any time regardless of the /MT_CTS state.
/TIME
Input
The /TIME pin can be used for triggering a timestamp packet. Its usage is optional.
Table 15