Intel SR1640TH SR1640THNA Manual Do Utilizador

Intel® Server System SR1640TH TPS 

Power Sub-System 

Revision 1.0 

 

 

69 

Intel order number: E94847-001 

The PSMC device in the power supply shall derive its power of the 5Vsb output on the 
system side of the O’ring device and shall be grounded to return.  

It shall be located at the address set by the A0 and A1 pins. 

Refer to the specification posted on 

 and 

 website for 

details on the power supply monitoring interface requirements and refer to followed section 
of supported features. The below table reflect the power module addresses complying with 
the position in the housing. 

 

The power supply shall support electronic access of FRU information over an I

2

C bus. Four 

pins at the power supply connector are allocated for this. They are named SCL, SDA, A0, A1. 
SCL is serial clock. SDA is serial data. These two bidirectional signals forms the basic 
communication lines over the I

2

C bus. A0, A1 are input address lines to the power supply. 

The backplane defines the state of these lines such that the address to the power supply is 
unique within the system. The resulting I

2

C address shall be per the table below. 

The device used for this shall be powered from a 5V bias voltage derived from the +5 VSB 
output . No pull-up resistors shall be on SCL or SDA inside the power supply.  

FRU data shall be stored starting in address location 8000h through 80FFh(ref). The FRU 
data format shall be compliant with the IPMI specifications. The current versions of these 
specifications are available at: 

 

There will be a bi-color LED to indicate power supply status as shown below; 

Power supply condition 

Power supply LED 

No AC power to PSU 

OFF 

AC present/only standby output on 

Flashing GREEN 

Power supply DC output ON and OK 

GREEN 

Power supply failure 

RED 

Power supply warning 

Flashing RED/GREEN 

 

The PSMC monitoring and control function set shall comply to the PMBus Spec. Rev. 1.1 
and above, which can be downloaded from the 

.  

The device in the power supply is compatible with both the SMBus 2.0 “high power” 
specification for I

2

C Vdd based power and drive (for Vdd = 3.3V). This bus operates at 3.3 V 

but is tolerant of 5 V signaling. It also operates at full 100 kbps SMBus speed without using 
clock stretching to slow down the bus. 

PDB position and power 

module address 

PM1/B0h 

PM2/B2h 

PM3/B4h 

PM4/B6h 

Pin A0 

0 1  0  1 

Pin A1 

0 0  1  1