Microchip Technology MCP4018T-104E/LT Linear IC SC-70-6 MCP4018T-104E/LT Ficha De Dados

© 2009 Microchip Technology Inc.

DS22147A-page 33

A 2-wire I

2

C serial protocol is used to write or read the

digital potentiometer’s wiper register. The I

2

C protocol

utilizes the SCL input pin and SDA input/output pin.
The I

2

C serial interface supports the following features. 

• Slave mode of operation
• 7-bit addressing
• The following clock rate modes are supported:

- Standard mode, bit rates up to 100 kb/s
- Fast mode, bit rates up to 400 kb/s

• Support Multi-Master Applications
The serial clock is generated by the Master.
The I

2

C Module is compatible with the Phillips I

2

C

specification. Phillips only defines the field types, field
lengths, timings, etc. of a frame. The frame content
defines the behavior of the device. The frame content
for the MCP4017, MCP4018, and MCP4019 devices
are defined in this section of the Data Sheet.

 shows a typical I

2

C bus configurations.

Refer to Section 2.0 “Typical Performance Curves”,
AC/DC Electrical Characteristics table for detailed input
threshold and timing specifications.

I

2

C specifications require active low, passive high

functionality on devices interfacing to the bus. Since
devices may be operating on separate power supply
sources, ESD clamping diodes are not permitted. The
specification recommends using open drain transistors
tied to V

SS

 (common) with a pull-up resistor. The

specification makes some general recommendations
on the size of this pull-up, but does not specify the
exact value since bus speeds and bus capacitance
impacts the pull-up value for optimum system
performance.
Common pull-up values range from 1 k

Ω

 to a max of

~10 k

Ω

. Power sensitive applications tend to choose

higher values to minimize current losses during
communication but these applications also typically
utilize lower V

DD

.

The SDA and SCL float (are not driving) when the
device is powered down. 
A "glitch" filter is on the SCL and SDA pins when the pin
is an input. When these pins are an output, there is a
slew rate control of the pin that is independent of device
frequency.

5.1.1

SLOPE CONTROL

The device implements slope control on the SDA
output. The slope control is defined by the fast mode
specifications.
For Fast (FS) mode, the device has spike suppression
and Schmidt trigger inputs on the SDA and SCL pins.

Single I

2

C Bus Configuration

Host

Controller

Device 1

Device 3

Device n

Device 2

Device 4