Manuais de utilizador para Microchip Technology MCP4018T-104E/LT Linear IC SC-70-6

índice analítico

• 1.0 Electrical Characteristics

  3
  • 1.1 I2C Mode Timing Waveforms and Requirements

    9
    • FIGURE 1-1: I2C Bus Start/Stop Bits Timing Waveforms.

      9
    • TABLE 1-1: I2C Bus Start/Stop Bits Requirements

      9
    • FIGURE 1-2: I2C Bus Data Timing.

      9
    • TABLE 1-2: I2C Bus Data Requirements (Slave Mode)

      10
• 2.0 Typical Performance Curves

  13
  • FIGURE 2-1: Interface Active Current (IDD) vs. SCL Frequency (fSCL) and Temperature (VDD = 1.8V, 2.7V and 5.5V).

    13
  • FIGURE 2-2: Interface Inactive Current (ISHDN) vs. Temperature and VDD. (VDD = 1.8V, 2.7V and 5.5V).

    13
  • FIGURE 2-3: 5.0 kW : Pot Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 5.5V). (A = VDD, B = VSS).

    14
  • FIGURE 2-4: 5.0 kW : Pot Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 2.7V). (A = VDD, B = VSS)

    14
  • FIGURE 2-5: 5.0 kW : Pot Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 1.8V). (A = VDD, B = VSS)

    14
  • FIGURE 2-6: 5.0 kW : Rheo Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 5.5V).(IW = 1.4mA, B = VSS)

    14
  • FIGURE 2-7: 5.0 kW : Rheo Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 2.7V).(IW = 450uA, B = VSS)

    14
  • FIGURE 2-8: 5.0 kW : Rheo Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 1.8V). (IW = TBD, B = VSS)

    14
  • FIGURE 2-9: 5.0 kW : Full Scale Error (FSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V).

    15
  • FIGURE 2-10: 5.0 kW : Zero Scale Error (ZSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V).

    15
  • FIGURE 2-11: 5.0 kW : Nominal Resistance (W) vs. Temperature and VDD.

    15
  • FIGURE 2-12: 5.0 kW : RBW Tempco DRWB / DT vs. Code.

    15
  • FIGURE 2-13: 5.0 kW : Power-Up Wiper Response Time.

    15
  • FIGURE 2-14: 5.0 kW : Digital Feedthrough (SCL signal coupling to Wiper pin).

    15
  • FIGURE 2-15: 5.0 kW : Write Wiper (40h ® 3Fh) Settling Time (VDD=5.5V).

    16
  • FIGURE 2-16: 5.0 kW : Write Wiper (40h ® 3Fh) Settling Time (VDD=2.7V).

    16
  • FIGURE 2-17: 5.0 kW : Write Wiper (40h ® 3Fh) Settling Time (VDD=1.8V).

    16
  • FIGURE 2-18: 5.0 kW : Write Wiper (FFh ® 00h) Settling Time (VDD=5.5V).

    16
  • FIGURE 2-19: 5.0 kW : Write Wiper (FFh ® 00h) Settling Time (VDD=2.7V).

    16
  • FIGURE 2-20: 5.0 kW : Write Wiper (FFh ® 00h) Settling Time (VDD=1.8V).

    16
  • FIGURE 2-21: 10 kW Pot Mode : RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 5.5V). (A = VDD, B = VSS)

    17
  • FIGURE 2-22: 10 kW Pot Mode : RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 2.7V). (A = VDD, B = VSS)

    17
  • FIGURE 2-23: 10 kW Pot Mode : RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 1.8V). (A = VDD, B = VSS)

    17
  • FIGURE 2-24: 10 kW Rheo Mode : RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 5.5V).(IW = 450uA, B = VSS)

    17
  • FIGURE 2-25: 10 kW Rheo Mode : RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 2.7V).(IW = 210uA, B = VSS)

    17
  • FIGURE 2-26: 10 kW Rheo Mode : RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 1.8V). (IW = TBD, B = VSS)

    17
  • FIGURE 2-27: 10 kW : Full Scale Error (FSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V).

    18
  • FIGURE 2-28: 10 kW : Zero Scale Error (ZSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V).

    18
  • FIGURE 2-29: 10 kW : Nominal Resistance (W) vs. Temperature and VDD.

    18
  • FIGURE 2-30: 10 kW : RBW Tempco DRWB / DT vs. Code.

    18
  • FIGURE 2-31: 10 kW : Power-Up Wiper Response Time.

    18
  • FIGURE 2-32: 10 kW : Digital Feedthrough (SCL signal coupling to Wiper pin).

    18
  • FIGURE 2-33: 10 kW : Write Wiper (40h ® 3Fh) Settling Time (VDD=5.5V).

    19
  • FIGURE 2-34: 10 kW : Write Wiper (40h ® 3Fh) Settling Time (VDD=2.7V).

    19
  • FIGURE 2-35: 10 kW : Write Wiper (40h ® 3Fh) Settling Time (VDD=1.8V).

    19
  • FIGURE 2-36: 10 kW : Write Wiper (FFh ® 00h) Settling Time (VDD=5.5V).

    19
  • FIGURE 2-37: 10 kW : Write Wiper (FFh ® 00h) Settling Time (VDD=2.7V).

    19
  • FIGURE 2-38: 10 kW : Write Wiper (FFh ® 00h) Settling Time (VDD=1.8V).

    19
  • FIGURE 2-39: 50 kW Pot Mode : RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 5.5V).

    20
  • FIGURE 2-40: 50 kW Pot Mode : RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 2.7V).

    20
  • FIGURE 2-41: 50 kW Pot Mode : RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 1.8V).

    20
  • FIGURE 2-42: 50 kW Rheo Mode : RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 5.5V).(IW = 90uA, B = VSS)

    20
  • FIGURE 2-43: 50 kW Rheo Mode : RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 2.7V).(IW = 45uA, B = VSS)

    20
  • FIGURE 2-44: 50 kW Rheo Mode : RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 1.8V). (IW = TBD, B = VSS)

    20
  • FIGURE 2-45: 50 kW : Full Scale Error (FSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V).

    21
  • FIGURE 2-46: 50 kW : Zero Scale Error (ZSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V).

    21
  • FIGURE 2-47: 50 kW : Nominal Resistance (W) vs. Temperature and VDD.

    21
  • FIGURE 2-48: 50 kW : RBW Tempco DRWB / DT vs. Code.

    21
  • FIGURE 2-49: 50 kW : Power-Up Wiper Response Time.

    21
  • FIGURE 2-50: 50 kW : Digital Feedthrough (SCL signal coupling to Wiper pin).

    21
  • FIGURE 2-51: 50 kW : Write Wiper (40h ® 3Fh) Settling Time (VDD=5.5V).

    22
  • FIGURE 2-52: 50 kW : Write Wiper (40h ® 3Fh) Settling Time (VDD=2.7V).

    22
  • FIGURE 2-53: 50 kW : Write Wiper (40h ® 3Fh) Settling Time (VDD=1.8V).

    22
  • FIGURE 2-54: 50 kW : Write Wiper (FFh ® 00h) Settling Time (VDD=5.5V).

    22
  • FIGURE 2-55: 50 kW : Write Wiper (FFh ® 00h) Settling Time (VDD=2.7V).

    22
  • FIGURE 2-56: 50 kW : Write Wiper (FFh ® 00h) Settling Time (VDD=1.8V).

    22
  • FIGURE 2-57: 100 kW Pot Mode : RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 5.5V).

    23
  • FIGURE 2-58: 100 kW Pot Mode : RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 2.7V).

    23
  • FIGURE 2-59: 100 kW Pot Mode : RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 1.8V).

    23
  • FIGURE 2-60: 100 kW Rheo Mode : RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 5.5V). (IW = 45uA, B = VSS)

    23
  • FIGURE 2-61: 100 kW Rheo Mode : RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 2.7V). (IW = 21uA, B = VSS)

    23
  • FIGURE 2-62: 100 kW Rheo Mode : RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 1.8V). (IW = TBD, B = VSS)

    23
  • FIGURE 2-63: 100 kW : Full Scale Error (FSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V).

    24
  • FIGURE 2-64: 100 kW : Zero Scale Error (ZSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V).

    24
  • FIGURE 2-65: 100 kW : Nominal Resistance (W) vs. Temperature and VDD.

    24
  • FIGURE 2-66: 100 kW : RBW Tempco DRWB / DT vs. Code.

    24
  • FIGURE 2-67: 100 kW : Power-Up Wiper Response Time.

    24
  • FIGURE 2-68: 100 kW : Digital Feedthrough (SCL signal coupling to Wiper pin).

    24
  • FIGURE 2-69: 100 kW : Write Wiper (40h ® 3Fh) Settling Time (VDD = 5.5V).

    25
  • FIGURE 2-70: 100 kW : Write Wiper (40h ® 3Fh) Settling Time (VDD = 2.7V).

    25
  • FIGURE 2-71: 100 kW : Write Wiper (40h ® 3Fh) Settling Time (VDD = 1.8V).

    25
  • FIGURE 2-72: 100 kW : Write Wiper (FFh ® 00h) Settling Time (VDD = 5.5V).

    25
  • FIGURE 2-73: 100 kW : Write Wiper (FFh ® 00h) Settling Time (VDD = 2.7V).

    25
  • FIGURE 2-74: 100 kW : Write Wiper (FFh ® 00h) Settling Time (VDD = 1.8V).

    25
  • FIGURE 2-75: VIH (SCL, SDA) vs. VDD and Temperature.

    26
  • FIGURE 2-76: VIL (SCL, SDA) vs. VDD and Temperature.

    26
  • FIGURE 2-77: VOL (SDA) vs. VDD and Temperature.

    26
  • FIGURE 2-78: POR/BOR Trip point vs. VDD and Temperature.

    26
  • FIGURE 2-79: 5 kW – Gain vs. Frequency (-3dB).

    27
  • FIGURE 2-80: 10 kW – Gain vs. Frequency (-3dB).

    27
  • FIGURE 2-81: 50 kW – Gain vs. Frequency (-3dB).

    27
  • FIGURE 2-82: 100 kW – Gain vs. Frequency (-3dB).

    27
  • 2.1 Test Circuits

    27
    • FIGURE 2-83: Gain vs. Frequency Test (-3dB).

      27
• 3.0 Pin Descriptions

  29
  • TABLE 3-1: Pinout Description for The MCP4017/18/19

    29
  • 3.1 Positive Power Supply Input (VDD)

    30
  • 3.2 Ground (VSS)

    30
  • 3.3 I2C Serial Clock (SCL)

    30
  • 3.4 I2C Serial Data (SDA)

    30
  • 3.5 Potentiometer Terminal B

    30
  • 3.6 Potentiometer Wiper (W) Terminal

    30
  • 3.7 Potentiometer Terminal A

    30
• 4.0 General Overview

  31
  • 4.1 POR/BOR Operation

    31
    • TABLE 4-1: Device functionality at each VDD Region (Note 1)

      32
    • FIGURE 4-1: Power-up and Brown-out.

      32
• 5.0 Serial Interface - I2C Module

  33
  • FIGURE 5-1: Typical Application I2C Bus Configurations.

    33
  • 5.1 I2C I/O Considerations

    33
  • 5.2 I2C Bit Definitions

    34
    • FIGURE 5-2: Start Bit.

      34
    • FIGURE 5-3: Data Bit.

      34
    • FIGURE 5-4: Acknowledge Waveform.

      34
    • TABLE 5-1: MCP4017/18/19 A / A Responses

      34
    • FIGURE 5-5: Repeat Start Condition Waveform.

      34
    • FIGURE 5-6: Stop Condition Receive or Transmit Mode.

      35
    • FIGURE 5-7: Typical 16-bit I2C Waveform Format.

      35
    • FIGURE 5-8: I2C Data States and Bit Sequence.

      35
    • FIGURE 5-9: Slave Address Bits in the I2C Control Byte.

      36
    • TABLE 5-2: Device I2C Address

      36
    • FIGURE 5-10: General Call Formats.

      36
  • 5.3 Software Reset Sequence

    37
    • FIGURE 5-11: Software Reset Sequence Format.

      37
  • 5.4 Serial Commands

    37
    • FIGURE 5-12: I2C Write Command Format.

      38
    • FIGURE 5-13: I2C Read Command Format.

      39
    • FIGURE 5-14: I2C Communication Behavior.

      40
• 6.0 Resistor Network

  41
  • 6.1 Resistor Ladder Module

    41
    • FIGURE 6-1: Resistor Network Block Diagram.

      41
    • TABLE 6-1: Wiper Setting MAP

      41
    • TABLE 6-2: Step Resistances

      42
    • TABLE 6-3: Default FACTORY SETTINGS Selection

      42
  • 6.2 Resistor Configurations

    43
    • FIGURE 6-2: Rheostat Configuration.

      43
    • FIGURE 6-3: Potentiometer Configuration.

      43
  • 6.3 Wiper Resistance

    44
    • FIGURE 6-4: Relationship of Wiper Resistance (RW) to Voltage.

      44
    • TABLE 6-4: Typical Step Resistances and relationship to Wiper Resistance

      44
  • 6.4 Operational Characteristics

    45
    • FIGURE 6-5: INL Accuracy.

      45
    • FIGURE 6-6: DNL Accuracy.

      45
    • FIGURE 6-7: RBW.

      46
• 7.0 Design Considerations

  47
  • 7.1 Power Supply Considerations

    47
    • FIGURE 7-1: Typical Microcontroller Connections.

      47
  • 7.2 Layout Considerations

    47
• 8.0 Applications Examples

  49
  • 8.1 Set Point Threshold Trimming

    49
    • FIGURE 8-1: Using the Digital Potentiometer to Set a Precise Output Voltage.

      49
    • FIGURE 8-2: Set Point or Threshold Calibration.

      49
  • 8.2 Operational Amplifier Applications

    50
    • FIGURE 8-3: Trimming Offset and Gain in a Non-Inverting Amplifier.

      50
    • FIGURE 8-4: Programmable Filter.

      50
  • 8.3 Temperature Sensor Applications

    51
    • FIGURE 8-5: Thermistor Calibration using a Digital Potentiometer in a Rheostat Configuration.

      51
    • FIGURE 8-6: Thermistor Calibration using a Digital Potentiometer in a Potentiometer Configuration.

      51
  • 8.4 Wheatstone Bridge Trimming

    52
    • FIGURE 8-7: Wheatstone Bridge Trimming.

      52
• 9.0 Development support

  53
  • 9.1 Development Tools

    53
  • 9.2 Technical Documentation

    53
    • TABLE 9-1: Technical Documentation

      53
• 10.0 Packaging Information

  55
  • 10.1 Package Marking Information

    55