Microchip Technology MCP4018T-104E/LT Linear IC SC-70-6 MCP4018T-104E/LT Ficha De Dados

© 2009 Microchip Technology Inc.

DS22147A-page 37

At times it may become necessary to perform a
Software Reset Sequence to ensure the MCP4017/18/
19 device is in a correct and known I

2

C Interface state.

This only resets the I

2

C state machine.

This is useful if the MCP4017/18/19 device powers up
in an incorrect state (due to excessive bus noise, etc),
or if the Master Device is reset during communication.

 shows the communication sequence to

software reset the device.

The 1st Start bit will cause the device to reset from a
state in which it is expecting to receive data from the
Master Device.In this mode, the device is monitoring
the data bus in Receive mode and can detect the Start
bit forces an internal Reset. 
The nine bits of ‘1’ are used to force a Reset of those
devices that could not be reset by the previous Start bit.
This occurs only if the MCP4017/18/19 is driving an A
on the I

2

C bus, or is in output mode (from a Read

command) and is driving a data bit of ‘0’ onto the I

2

C

bus. In both of these cases, the previous Start bit could
not be generated due to the MCP4017/18/19 holding
the bus low. By sending out nine ‘1’ bits, it is ensured
that the device will see a A (the Master Device does not
drive the I

2

C bus low to acknowledge the data sent by

the MCP4017/18/19), which also forces the MCP4017/
18/19 to reset.
The 2nd Start bit is sent to address the rare possibility
of an erroneous write. This could occur if the Master
Device was reset while sending a Write command to
the MCP4017/18/19, AND then as the Master Device
returns to normal operation and issues a Start condition
while the MCP4017/18/19 is issuing an A. In this case
if the 2nd Start bit is not sent (and the Stop bit was sent)
the MCP4017/18/19 could initiate a write cycle.    

The Stop bit terminates the current I

2

C bus activity. The

MCP4017/18/19 wait to detect the next Start condition.
This sequence does not effect any other I

2

C devices

which may be on the bus, as they should disregard this
as an invalid command.

The MCP4017/18/19 devices support 2 serial
commands. These commands are: 
•

•

This technique should be supported by
any I

2

C compliant device. The 24xxxx I

2

C

Serial EEPROM devices support this tech-
nique, which is documented in AN1028.

The potential for this erroneous write
ONLY occurs if the Master Device is reset
while sending a Write command to the
MCP4017/18/19. 

        

S

‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’

S

P

Start

bit

Nine bits of ‘1’

Start bit

Stop bit