Microchip Technology AC244055 Ficha De Dados
PIC16(L)F1938/9
DS40001574C-page 180
2011-2013 Microchip Technology Inc.
19.2
Latch Output
The SRQEN and SRNQEN bits of the SRCON0 regis-
ter control the Q and Q latch outputs. Both of the SR
Latch outputs may be directly output to an I/O pin at the
same time. The Q latch output pin function can be
moved to an alternate pin using the SRNQSEL bit of
the APFCON register.
The applicable TRIS bit of the corresponding port must
be cleared to enable the port pin output driver.
ter control the Q and Q latch outputs. Both of the SR
Latch outputs may be directly output to an I/O pin at the
same time. The Q latch output pin function can be
moved to an alternate pin using the SRNQSEL bit of
the APFCON register.
The applicable TRIS bit of the corresponding port must
be cleared to enable the port pin output driver.
19.3
Effects of a Reset
Upon any device Reset, the SR Latch output is not ini-
tialized to a known state. The user’s firmware is
responsible for initializing the latch output before
enabling the output pins.
tialized to a known state. The user’s firmware is
responsible for initializing the latch output before
enabling the output pins.
FIGURE 19-1:
SR LATCH SIMPLIFIED BLOCK DIAGRAM
SRPS
S
R
Q
Q
Note 1:
If R = 1 and S = 1 simultaneously, Q = 0, Q = 1
2:
Pulse generator causes a 1 Q-state pulse width.
3:
Name denotes the connection point at the comparator output.
Pulse
Gen
(2)
SR
Latch
Latch
(1)
SRQEN
SRSPE
SRSC2E
SRSCKE
SRCLK
sync_C2OUT
(3)
SRSC1E
sync_C1OUT
(3)
SRPR
Pulse
Gen
(2)
SRRPE
SRRC2E
SRRCKE
SRCLK
sync_C2OUT
(3)
SRRC1E
sync_C1OUT
(3)
SRLEN
SRNQEN
SRLEN
SRQ
SRNQ
SRI
SRI