Manual Do Utilizadoríndice analíticoEmulation Extension Pak (EEP) and Emulation Header User's Guide1Table of Contents3Chapter 1. EEP and Emulation Header Overview5Chapter 2. Emulation Header Features13Chapter 3. Emulation Header List25Chapter 4. Emulation Header Target Footprints35Chapter 5. Emulation Header Connections37Worldwide Sales and Service44Tamanho: 900 KBPáginas: 44Language: EnglishAbrir o manual
Ficha De Dadosíndice analíticoHigh-Performance RISC CPU:1Special Microcontroller Features:1PIC16LF193X Low-Power Features:1Peripheral Features:1Peripheral Features (Continued):2Most Current Data Sheet9Errata9Customer Notification System91.0 Device Overview11TABLE 1-1: Device Peripheral Summary11FIGURE 1-1: PIC16(L)F1938/9 Block Diagram12TABLE 1-2: PIC16(L)F1938/9 Pinout Description132.0 Enhanced Mid-range CPU192.1 Automatic Interrupt Context Saving192.2 16-Level Stack with Overflow and Underflow192.3 File Select Registers192.4 Instruction Set19FIGURE 2-1: Core Block Diagram203.0 Memory Organization213.1 Program Memory Organization21TABLE 3-1: Device Sizes and Addresses21FIGURE 3-1: Program Memory Map And Stack For 16 KW Parts223.1.1 Reading Program Memory as Data22EXAMPLE 3-1: RETLW Instruction22EXAMPLE 3-2: Accessing Program Memory Via FSR233.2 Data Memory Organization233.2.1 Core Registers233.3 Register Definitions: Status24Register 3-1: STATUS: STATUS Register243.3.1 Special Function Register253.3.2 General Purpose RAM253.3.3 Common RAM25FIGURE 3-2: Banked Memory Partitioning253.3.4 Device Memory Maps25TABLE 3-2: Memory Map Tables25TABLE 3-3: PIC16(L)F1938/9 Memory Map, Banks 0-726TABLE 3-4: PIC16(L)F1938/9 Memory Map, Banks 8-1527TABLE 3-5: PIC16(L)F1938/9 Memory Map, Banks 16-2328TABLE 3-6: PIC16(L)F1938/9 Memory Map, Banks 24-3129TABLE 3-7: PIC16(L)F1938 Memory Map, Bank 1530TABLE 3-8: PIC16(L)F1939 Memory Map, Bank 1530TABLE 3-9: PIC16(L)F1938/9 Memory Map, Bank 31313.3.5 Special Function Registers Summary31TABLE 3-10: Special Function Register Summary323.4 PCL and PCLATH46FIGURE 3-3: Loading Of PC in Different Situations463.4.1 Modifying PCL463.4.2 Computed GOTO463.4.3 Computed Function Calls463.4.4 Branching463.5 Stack473.5.1 Accessing the Stack47FIGURE 3-4: Accessing the Stack Example 147FIGURE 3-5: Accessing the Stack Example 248FIGURE 3-6: Accessing the Stack Example 348FIGURE 3-7: Accessing the Stack Example 4493.5.2 Overflow/Underflow Reset493.6 Indirect Addressing49FIGURE 3-8: Indirect Addressing503.6.1 Traditional Data Memory51FIGURE 3-9: Traditional Data Memory Map513.6.2 Linear Data Memory52FIGURE 3-10: Linear Data Memory Map523.6.3 Program Flash Memory52FIGURE 3-11: Program Flash Memory Map524.0 Device Configuration534.1 Configuration Words534.2 Register Definitions: Configuration54Register 4-1: Configuration Word 154Register 4-2: Configuration Word 2564.3 Code Protection574.3.1 Program Memory Protection574.3.2 Data EEPROM Protection574.4 Write Protection574.5 User ID574.6 Device ID and Revision ID584.7 Register Definitions: Device ID58Register 4-3: DEVICEID: Device ID Register(1)585.0 Oscillator Module (With Fail-Safe Clock Monitor)595.1 Overview59FIGURE 5-1: Simplified PIC® MCU Clock Source Block Diagram605.2 Clock Source Types615.2.1 External Clock Sources61FIGURE 5-2: External Clock (EC) Mode Operation61FIGURE 5-3: Quartz Crystal Operation (LP, XT or HS Mode)62FIGURE 5-4: Ceramic Resonator Operation (XT or HS Mode)62FIGURE 5-5: Quartz Crystal Operation (Timer1 Oscillator)63FIGURE 5-6: External RC Modes635.2.2 Internal Clock Sources64FIGURE 5-7: Internal Oscillator Switch Timing675.3 Clock Switching685.3.1 System Clock Select (SCS) BitS685.3.2 Oscillator Start-up Time-out Status (OSTS) Bit685.3.3 Timer1 Oscillator685.3.4 Timer1 Oscillator Ready (T1OSCR) Bit685.4 Two-Speed Clock Start-up Mode695.4.1 Two-Speed Start-up Mode Configuration69TABLE 5-1: Oscillator Switching Delays695.4.2 Two-Speed Start-up Sequence705.4.3 Checking Two-Speed Clock Status70FIGURE 5-8: Two-Speed Start-up705.5 Fail-Safe Clock Monitor71FIGURE 5-9: FSCM Block Diagram715.5.1 Fail-Safe Detection715.5.2 Fail-Safe Operation715.5.3 Fail-Safe Condition Clearing715.5.4 Reset or Wake-up from Sleep71FIGURE 5-10: FSCM Timing Diagram725.6 Register Definitions: Oscillator Control73Register 5-1: OSCCON: Oscillator Control Register73Register 5-2: OSCSTAT: Oscillator Status Register74Register 5-3: OSCTUNE: Oscillator Tuning Register75TABLE 5-2: Summary of Registers Associated with Clock Sources75TABLE 5-3: Summary of Configuration Word with Clock Sources756.0 Resets77FIGURE 6-1: Simplified Block Diagram Of On-Chip Reset Circuit776.1 Power-on Reset (POR)786.1.1 Power-up Timer (PWRT)786.2 Brown-Out Reset (BOR)78TABLE 6-1: BOR Operating Modes786.2.1 BOR is Always On786.2.2 BOR is Off in Sleep786.2.3 BOR Controlled by Software78FIGURE 6-2: Brown-Out Situations796.3 Register Definitions: BOR Control79Register 6-1: BORCON: Brown-out Reset Control Register796.4 MCLR80TABLE 6-2: MCLR Configuration806.4.1 MCLR Enabled806.4.2 MCLR Disabled806.5 Watchdog Timer (WDT) Reset806.6 RESET Instruction806.7 Stack Overflow/Underflow Reset806.8 Programming Mode Exit806.9 Power-Up Timer806.10 Start-up Sequence80FIGURE 6-3: Reset Start-Up Sequence816.11 Determining the Cause of a Reset82TABLE 6-3: Reset Status Bits and Their Significance82TABLE 6-4: Reset Condition for Special Registers(2)826.12 Power Control (PCON) Register836.13 Register Definitions: Power Control (PCON)83Register 6-2: PCON: Power Control Register83TABLE 6-5: Summary Of Registers Associated With Resets847.0 Interrupts85FIGURE 7-1: Interrupt Logic857.1 Operation867.2 Interrupt Latency86FIGURE 7-2: Interrupt Latency87FIGURE 7-3: INT Pin Interrupt Timing887.3 Interrupts During Sleep897.4 INT Pin897.5 Automatic Context Saving897.6 Register Definitions: Interrupt Control90Register 7-1: INTCON: Interrupt Control Register90Register 7-2: PIE1: Peripheral Interrupt Enable Register 191Register 7-3: PIE2: Peripheral Interrupt Enable Register 292Register 7-4: PIE3: Peripheral Interrupt Enable Register 393Register 7-5: PIR1: Peripheral Interrupt Request Register 194Register 7-6: PIR2: Peripheral Interrupt Request Register 295Register 7-7: PIR3: Peripheral Interrupt Request Register 396TABLE 7-1: Summary of Registers Associated with Interrupts978.0 Low Dropout (LDO) Voltage Regulator99TABLE 8-1: VCAPEN<1:0> Select Bits99TABLE 8-2: Summary of Configuration Word with LDO999.0 Power-Down Mode (Sleep)1019.1 Wake-up from Sleep1019.1.1 Wake-up Using Interrupts102FIGURE 9-1: Wake-Up From Sleep Through Interrupt102TABLE 9-1: Summary of Registers Associated with Power-Down Mode10210.0 Watchdog Timer103FIGURE 10-1: Watchdog Timer Block Diagram10310.1 Independent Clock Source10410.2 WDT Operating Modes10410.2.1 WDT is Always On10410.2.2 WDT is Off in Sleep10410.2.3 WDT Controlled By Software104TABLE 10-1: WDT Operating Modes10410.3 Time-Out Period10410.4 Clearing the WDT10410.5 Operation During Sleep104TABLE 10-2: WDT Clearing Conditions10410.6 Register Definitions: Watchdog Control105Register 10-1: WDTCON: Watchdog Timer Control Register105TABLE 10-3: Summary of Registers Associated with Watchdog Timer106TABLE 10-4: Summary of Configuration Word with Watchdog Timer10611.0 Data EEPROM and Flash Program Memory Control10711.1 EEADRL and EEADRH Registers10711.1.1 EECON1 and EECON2 Registers10711.2 Using the Data EEPROM10811.2.1 Reading the Data EEPROM Memory108EXAMPLE 11-1: Data EEPROM Read10811.2.2 Writing to the Data EEPROM Memory10811.2.3 Protection Against Spurious Write10811.2.4 Data EEPROM Operation During Code-Protect108EXAMPLE 11-2: Data EEPROM Write109FIGURE 11-1: Flash Program Memory Read Cycle Execution10911.3 Flash Program Memory Overview11011.3.1 Reading the Flash Program Memory110TABLE 11-1: Flash Memory Organization By Device110EXAMPLE 11-3: Flash Program Memory Read11111.3.2 Erasing Flash Program Memory11211.3.3 Writing to Flash Program Memory112FIGURE 11-2: Block WRITES to Flash Program Memory with 8 Write Latches113EXAMPLE 11-4: Erasing One Row of Program Memory114EXAMPLE 11-5: Writing to Flash Program Memory11511.4 Modifying Flash Program Memory11611.5 User ID, Device ID and Configuration Word Access116TABLE 11-2: User ID, Device ID and Configuration Word Access (cfgs = 1)11611.6 Write Verify117EXAMPLE 11-6: EEPROM Write Verify11711.7 Register Definitions: EEPROM and Flash Control118Register 11-1: EEDATL: EEPROM Data Low-Byte Register118Register 11-2: EEDATH: EEPROM Data High-Byte Register118Register 11-3: EEADRL: EEPROM Address Low-Byte Register118Register 11-4: EEADRH: EEPROM Address High-Byte Register118Register 11-5: EECON1: EEPROM Control 1 Register119Register 11-6: EECON2: EEPROM Control 2 Register120TABLE 11-3: Summary of Registers Associated with Data EEPROM12012.0 I/O Ports121TABLE 12-1: Port Availability Per Device121TABLE 12-2: Port Availability per Device121FIGURE 12-1: Generic I/O Port Operation121EXAMPLE 12-1: Initializing PORTA12112.1 Alternate Pin Function12212.2 Register Definitions: Alternate Pin Function Control123Register 12-1: APFCON: Alternate Pin Function Control Register12312.3 PORTA Registers12412.3.1 ANSELA Register12412.3.2 PORTA Functions and Output Priorities124TABLE 12-3: PORTA Output Priority12412.4 Register Definitions: PORTA Control125Register 12-2: PORTA: PORTA Register125Register 12-3: TRISA: PORTA Tri-State Register125Register 12-4: LATA: PORTA Data Latch Register125Register 12-5: ANSELA: PORTA Analog Select Register126TABLE 12-4: Summary of Registers Associated with PORTA127TABLE 12-5: Summary of Configuration Word with PORTA12712.5 PORTB Registers12812.5.1 Weak Pull-Ups12812.5.2 Interrupt-on-Change12812.5.3 ANSELB Register12812.5.4 PORTB Functions and Output Priorities129TABLE 12-6: PORTB Output Priority12912.6 Register Definitions: PORTB Control130Register 12-6: PORTB: PORTB Register130Register 12-7: TRISB: PORTB Tri-State Register130Register 12-8: LATB: PORTB Data Latch Register130Register 12-9: ANSELB: PORTB Analog Select Register131Register 12-10: WPUB: WEAK PULL-up PORTB Register131TABLE 12-7: Summary of Registers Associated with PORTB13212.7 PORTC Registers13312.7.1 PORTC Functions and Output Priorities133TABLE 12-8: PORTC Output Priority13312.8 Register Definitions: PORTC Control134Register 12-11: PORTC: PORTC Register134Register 12-12: TRISC: PORTC Tri-State Register134Register 12-13: LATC: PORTC Data Latch Register134TABLE 12-9: Summary of Registers Associated with PORTC13512.9 PORTD Registers (PIC16(L)F1939 only)13612.9.1 ANSELD Register13612.9.2 PORTD Functions and Output Priorities136TABLE 12-10: PORTD Output Priority13612.10 Register Definitions: PORTD Control137Register 12-14: PORTD: PORTD Register(1)137Register 12-15: TRISD: PORTD Tri-State Register(1)137Register 12-16: LATD: PORTD Data Latch Register138Register 12-17: ANSELD: PORTD Analog Select Register(2)138TABLE 12-11: Summary of Registers Associated with PORTD(1)13812.11 PORTE Registers13912.11.1 ANSELE Register13912.11.2 PORTE Functions and Output Priorities139TABLE 12-12: PORTE Output Priority13912.12 Register Definitions: PORTE Control140Register 12-18: PORTE: PORTE Register140Register 12-19: TRISE: PORTE Tri-State Register140Register 12-20: LATE: PORTE Data Latch Register141Register 12-21: ANSELE: PORTE Analog Select Register141Register 12-22: WPUE: Weak Pull-uP PORTE Register142TABLE 12-13: Summary of Registers Associated with PORTE14213.0 Interrupt-On-Change14313.1 Enabling the Module14313.2 Individual Pin Configuration14313.3 Interrupt Flags14313.4 Clearing Interrupt Flags143EXAMPLE 13-1: Clearing Interrupt Flags (PORTA Example)14313.5 Operation in Sleep143FIGURE 13-1: Interrupt-On-Change Block Diagram14413.6 Register Definitions: Interrupt-On-Change145Register 13-1: IOCBP: Interrupt-on-Change Positive Edge Register145Register 13-2: IOCBN: Interrupt-on-Change Negative Edge Register145Register 13-3: IOCBF: Interrupt-on-Change Flag Register145TABLE 13-1: Summary of Registers Associated with Interrupt-on-Change14614.0 Fixed Voltage Reference (FVR)14714.1 Independent Gain Amplifiers14714.2 FVR Stabilization Period147FIGURE 14-1: Voltage Reference Block Diagram14714.3 Register Definitions: FVR Control148Register 14-1: FVRCON: Fixed Voltage Reference Control Register148TABLE 14-1: Summary of Registers Associated with Fixed Voltage Reference14815.0 Analog-to-Digital Converter (ADC) Module149FIGURE 15-1: ADC Block Diagram14915.1 ADC Configuration15015.1.1 Port Configuration15015.1.2 Channel Selection15015.1.3 ADC Voltage Reference15015.1.4 Conversion Clock150TABLE 15-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies151FIGURE 15-2: Analog-to-Digital Conversion Tad Cycles15115.1.5 Interrupts15215.1.6 Result Formatting152FIGURE 15-3: 10-Bit A/D Conversion Result Format15215.2 ADC Operation15315.2.1 Starting a Conversion15315.2.2 Completion of a Conversion15315.2.3 Terminating a Conversion15315.2.4 ADC Operation During Sleep15315.2.5 Special Event Trigger153TABLE 15-2: Special Event Trigger15315.2.6 A/D Conversion Procedure154EXAMPLE 15-1: A/D Conversion15415.3 Register Definitions: ADC Control155Register 15-1: ADCON0: A/D Control Register 0155Register 15-2: ADCON1: A/D Control Register 1156Register 15-3: ADRESH: ADC Result Register High (ADRESH) ADFM = 0157Register 15-4: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0157Register 15-5: ADRESH: ADC Result Register High (ADRESH) ADFM = 1158Register 15-6: ADRESL: ADC Result Register Low (ADRESL) ADFM = 115815.4 A/D Acquisition Requirements159EQUATION 15-1: Acquisition Time Example159FIGURE 15-4: Analog Input Model160FIGURE 15-5: ADC Transfer Function160TABLE 15-3: Summary of Registers Associated with ADC16116.0 Temperature Indicator Module16316.1 Circuit Operation163EQUATION 16-1: Vout Ranges163FIGURE 16-1: Temperature Circuit Diagram16316.2 Minimum Operating Vdd163TABLE 16-1: Recommended Vdd vs. Range16316.3 Temperature Output16316.4 ADC Acquisition Time163TABLE 16-2: Summary of Registers Associated with the Temperature Indicator16417.0 Digital-to-Analog Converter (DAC) Module16517.1 Output Voltage Selection165EQUATION 17-1: DAC Output Voltage16517.2 Ratiometric Output Level16517.3 DAC Voltage Reference Output165FIGURE 17-1: Digital-to-Analog Converter Block Diagram166FIGURE 17-2: Voltage Reference Output Buffer Example16617.4 Low-Power Voltage State16717.4.1 Output Clamped to Positive Voltage Source16717.4.2 Output Clamped to Negative Voltage Source167FIGURE 17-3: Output Voltage Clamping Examples16717.5 Operation During Sleep16717.6 Effects of a Reset16717.7 Register Definitions: DAC Control168Register 17-1: DACCON0: Voltage Reference Control Register 0168Register 17-2: DACCON1: Voltage Reference Control Register 1168TABLE 17-1: Summary of Registers Associated with the DAC Module16818.0 Comparator Module16918.1 Comparator Overview169FIGURE 18-1: Single Comparator169FIGURE 18-2: Comparator Module Simplified Block Diagram17018.2 Comparator Control17118.2.1 Comparator Enable17118.2.2 Comparator Output Selection17118.2.3 Comparator Output Polarity171TABLE 18-1: Comparator Output State vs. Input Conditions17118.2.4 Comparator Speed/Power Selection17118.3 Comparator Hysteresis17218.4 Timer1 Gate Operation17218.4.1 Comparator Output Synchronization17218.5 Comparator Interrupt17218.6 Comparator Positive Input Selection17218.7 Comparator Negative Input Selection17318.8 Comparator Response Time17318.9 Interaction with ECCP Logic17318.10 Analog Input Connection Considerations173FIGURE 18-3: Analog Input Model17418.11 Register Definitions: Comparator Control175Register 18-1: CMxCON0: Comparator cx Control Register 0175Register 18-2: CMxCON1: Comparator cx Control Register 1176Register 18-3: CMOUT: Comparator Output Register176TABLE 18-2: Summary of Registers Associated with Comparator Module17719.0 SR Latch17919.1 Latch Operation17919.2 Latch Output18019.3 Effects of a Reset180FIGURE 19-1: SR Latch Simplified Block Diagram180TABLE 19-1: SRCLK Frequency table18119.4 Register Definitions: SR Latch Control182Register 19-1: SRCON0: SR Latch Control 0 Register182Register 19-2: SRCON1: SR Latch Control 1 Register183TABLE 19-2: Summary of Registers Associated with SR Latch Module18320.0 Timer0 Module18520.1 Timer0 Operation18520.1.1 8-bit Timer Mode18520.1.2 8-Bit Counter Mode185FIGURE 20-1: Block Diagram of the Timer018520.1.3 Software Programmable Prescaler18620.1.4 Timer0 Interrupt18620.1.5 8-BIT COUNTER MODE SYNCHRONIZATION18620.1.6 Operation During Sleep18620.2 Register Definitions: Timer0 Control187Register 20-1: OPTION_REG: OPTION Register187TABLE 20-1: Summary of Registers Associated with Timer018721.0 Timer1 Module with Gate Control189FIGURE 21-1: Timer1 Block Diagram18921.1 Timer1 Operation190TABLE 21-1: Timer1 Enable Selections19021.2 Clock Source Selection19021.2.1 Internal Clock Source19021.2.2 External Clock Source190TABLE 21-2: Clock Source Selections19021.3 Timer1 Prescaler19121.4 Timer1 Oscillator19121.5 Timer1 Operation in Asynchronous Counter Mode19121.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode19121.6 Timer1 Gate19121.6.1 Timer1 Gate Enable191TABLE 21-3: Timer1 Gate Enable Selections19121.6.2 Timer1 Gate Source Selection192TABLE 21-4: Timer1 Gate Sources19221.6.3 Timer1 Gate Toggle Mode19221.6.4 Timer1 Gate Single-Pulse Mode19221.6.5 Timer1 Gate Value Status19221.6.6 Timer1 Gate Event Interrupt19221.7 Timer1 Interrupt19321.8 Timer1 Operation During Sleep19321.9 ECCP/CCP Capture/Compare Time Base19321.10 ECCP/CCP Special Event Trigger193FIGURE 21-2: Timer1 Incrementing Edge193FIGURE 21-3: Timer1 Gate Enable Mode194FIGURE 21-4: Timer1 Gate Toggle Mode194FIGURE 21-5: Timer1 Gate Single-Pulse Mode195FIGURE 21-6: Timer1 Gate Single-Pulse and Toggle Combined Mode19621.11 Register Definitions: Timer1 Control197Register 21-1: T1CON: Timer1 Control Register197Register 21-2: T1GCON: Timer1 Gate Control Register198TABLE 21-5: Summary of Registers Associated with Timer119922.0 Timer2/4/6 Modules201FIGURE 22-1: Timer2/4/6 Block Diagram20122.1 Timer2/4/6 Operation20222.2 Timer2/4/6 Interrupt20222.3 Timer2/4/6 Output20222.4 Timer2/4/6 Operation During Sleep20222.5 Register Definitions: Timer2/4/6 Control203Register 22-1: TxCON: Timer2/timer4/timer6 Control Register203TABLE 22-1: Summary of Registers Associated With Timer2/4/620423.0 Capture/Compare/PWM Modules205TABLE 23-1: PWM Resources20523.1 Capture Mode20623.1.1 CCP pin Configuration206FIGURE 23-1: Capture Mode Operation Block Diagram20623.1.2 Timer1 Mode Resource20623.1.3 Software Interrupt Mode20623.1.4 CCP Prescaler206EXAMPLE 23-1: Changing Between Capture Prescalers20623.1.5 Capture During Sleep20623.1.6 Alternate Pin Locations207TABLE 23-2: Summary of Registers Associated with Capture20723.2 Compare Mode208FIGURE 23-2: Compare Mode Operation Block Diagram20823.2.1 CCP Pin Configuration20823.2.2 Timer1 Mode Resource20823.2.3 Software Interrupt Mode20823.2.4 Special Event Trigger208TABLE 23-3: Special Event Trigger20823.2.5 Compare During Sleep20923.2.6 Alternate Pin Locations209TABLE 23-4: Summary of Registers Associated with Compare20923.3 PWM Overview21023.3.1 Standard PWM Operation210FIGURE 23-3: CCP PWM Output Signal210FIGURE 23-4: Simplified PWM Block Diagram21023.3.2 Setup for PWM Operation21123.3.3 Timer2/4/6 Timer Resource21123.3.4 PWM period211EQUATION 23-1: PWM Period21123.3.5 PWM Duty Cycle211EQUATION 23-2: Pulse Width211EQUATION 23-3: Duty Cycle Ratio21123.3.6 PWM Resolution212EQUATION 23-4: PWM Resolution212TABLE 23-5: Example PWM Frequencies and Resolutions (Fosc = 32 MHz)212TABLE 23-6: Example PWM Frequencies and Resolutions (Fosc = 20 MHz)212TABLE 23-7: Example PWM Frequencies and Resolutions (Fosc = 8 MHz)21223.3.7 Operation in Sleep Mode21323.3.8 Changes in System Clock Frequency21323.3.9 Effects of Reset21323.3.10 Alternate Pin Locations213TABLE 23-8: Summary of Registers Associated with Standard PWM21323.4 PWM (Enhanced Mode)214FIGURE 23-5: Example Simplified Block Diagram of the Enhanced PWM Mode214TABLE 23-9: Example Pin Assignments for Various PWM Enhanced Modes215FIGURE 23-6: Example PWM (Enhanced Mode) Output Relationships (Active-High State)215FIGURE 23-7: Example Enhanced PWM Output Relationships (Active-Low State)21623.4.1 Half-Bridge Mode217FIGURE 23-8: Example of Half-Bridge PWM Output217FIGURE 23-9: Example of Half-Bridge Applications21723.4.2 Full-Bridge Mode218FIGURE 23-10: Example of Full-Bridge Application218FIGURE 23-11: Example of Full-Bridge PWM Output219FIGURE 23-12: Example of PWM Direction Change220FIGURE 23-13: Example of PWM Direction Change at Near 100% Duty Cycle22123.4.3 Enhanced PWM Auto-shutdown mode222FIGURE 23-14: PWM Auto-shutdown With Firmware Restart (PxRSEN = 0)22223.4.4 Auto-Restart Mode223FIGURE 23-15: PWM Auto-Shutdown with Auto-Restart (PxRSEN = 1)22323.4.5 Programmable Dead-Band Delay Mode224FIGURE 23-16: Example of Half-Bridge PWM Output224FIGURE 23-17: Example of Half-Bridge Applications22423.4.6 PWM Steering Mode225FIGURE 23-18: Simplified Steering Block Diagram22523.4.7 Start-up Considerations226FIGURE 23-19: Example of Steering Event at End of Instruction (STRxSYNC = 0)226FIGURE 23-20: Example of Steering Event at Beginning of Instruction (STRxSYNC = 1)226TABLE 23-10: Summary of Registers Associated with Enhanced PWM22723.5 Register Definitions: CCP Control228Register 23-1: CCPXCON: CCPx Control Register228Register 23-2: CCPTMRS0: PWM Timer Selection Control Register 0229Register 23-3: CCPTMRS1: PWM Timer Selection Control Register 1230Register 23-4: CCPxAS: CCPx Auto-Shutdown Control Register231Register 23-5: PWMxCON: Enhanced PWM Control Register232Register 23-6: PSTRxCON: PWM Steering Control Register(1)23324.0 Master Synchronous Serial Port Module23524.1 Master SSP (MSSP) Module Overview235FIGURE 24-1: MSSP Block Diagram (SPI mode)235FIGURE 24-2: MSSP Block Diagram (I2C™ Master mode)236FIGURE 24-3: MSSP Block Diagram (I2C™ Slave mode)23724.2 SPI Mode Overview238FIGURE 24-4: SPI Master and Multiple Slave Connection23924.2.1 SPI Mode Registers23924.2.2 SPI Mode Operation240FIGURE 24-5: SPI Master/Slave Connection24024.2.3 SPI Master Mode241FIGURE 24-6: SPI Mode Waveform (Master Mode)24124.2.4 SPI SLAVE MODE24224.2.5 SLAVE SELECT SYNCHRONIZATION242FIGURE 24-7: SPI Daisy-Chain Connection243FIGURE 24-8: slave Select Synchronous Waveform243FIGURE 24-9: SPI Mode Waveform (Slave Mode With CKE = 0)244FIGURE 24-10: SPI Mode Waveform (SLAve Mode With CKE = 1)24424.2.6 SPI Operation in Sleep Mode245TABLE 24-1: Summary of Registers Associated with SPI Operation24524.3 I2C™ Mode Overview246FIGURE 24-11: I2C Master/ Slave Connection24624.3.1 CLOCK STRETCHING24724.3.2 ARBITRATION24724.4 I2C™ Mode Operation24724.4.1 Byte Format24724.4.2 Definition of I2C Terminology24724.4.3 SDA and SCL PINS24724.4.4 SDA Hold Time248TABLE 24-2: I2C Bus Terms24824.4.5 Start Condition24924.4.6 STOP condition24924.4.7 Restart Condition24924.4.8 START/STOP Condition Interrupt Masking249FIGURE 24-12: I2C START and STOP Conditions249FIGURE 24-13: I2C Restart Condition24924.4.9 Acknowledge Sequence25024.5 I2C Slave Mode Operation25024.5.1 Slave Mode Addresses25024.5.2 Slave Reception251FIGURE 24-14: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0)252FIGURE 24-15: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)253FIGURE 24-16: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1)254FIGURE 24-17: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1)25524.5.3 SLAVE Transmission256FIGURE 24-18: I2C Slave, 7-Bit Address, TRANSMISSION (AHEN = 0)257FIGURE 24-19: I2C Slave, 7-Bit Address, Transmission (AHEN = 1)25924.5.4 Slave mode 10-bit Address Reception26024.5.5 10-bit Addressing With Address Or Data Hold260FIGURE 24-20: I2C Slave, 10-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)261FIGURE 24-21: I2C Slave, 10-Bit Address, Reception (SeN = 0, AHEN = 1, DHEN = 0)262FIGURE 24-22: I2C Slave, 10-Bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0)26324.5.6 Clock Stretching26424.5.7 Clock Synchronization and the CKP bit264FIGURE 24-23: Clock Synchronization Timing26424.5.8 General Call Address Support265FIGURE 24-24: Slave Mode General Call Address Sequence26524.5.9 SSP Mask Register26524.6 I2C Master Mode26624.6.1 I2C Master Mode Operation26624.6.2 Clock Arbitration267FIGURE 24-25: Baud Rate Generator Timing with Clock Arbitration26724.6.3 WCOL Status Flag26724.6.4 I2C Master Mode Start Condition Timing268FIGURE 24-26: First Start Bit Timing26824.6.5 I2C Master Mode REPEATED Start Condition Timing269FIGURE 24-27: Repeat Start Condition Waveform26924.6.6 I2C Master Mode Transmission270FIGURE 24-28: I2C Master Mode Waveform (Transmission, 7 or 10-Bit Address)27124.6.7 I2C Master Mode Reception272FIGURE 24-29: I2C Master Mode Waveform (Reception, 7-Bit Address)27324.6.8 Acknowledge Sequence Timing27424.6.9 Stop Condition Timing274FIGURE 24-30: Acknowledge Sequence Waveform274FIGURE 24-31: Stop Condition Receive or Transmit Mode27424.6.10 Sleep Operation27524.6.11 Effects of a Reset27524.6.12 Multi-Master Mode27524.6.13 Multi -Master Communication, Bus Collision and Bus Arbitration275FIGURE 24-32: Bus Collision Timing for Transmit and Acknowledge275FIGURE 24-33: Bus Collision During Start Condition (SDA Only)276FIGURE 24-34: Bus Collision During Start Condition (SCL = 0)277FIGURE 24-35: BRG Reset Due to Sda Arbitration During Start Condition277FIGURE 24-36: Bus Collision During a Repeated Start Condition (Case 1)278FIGURE 24-37: Bus Collision During Repeated Start Condition (Case 2)278FIGURE 24-38: Bus Collision During a Stop Condition (Case 1)279FIGURE 24-39: Bus Collision During a Stop Condition (Case 2)279TABLE 24-3: Summary of Registers Associated with I2C™ Operation28024.7 Baud Rate Generator281FIGURE 24-40: Baud Rate Generator Block Diagram281TABLE 24-4: MSSP Clock Rate w/BRG28124.8 Register Definitions: MSSP Control282Register 24-1: SSPSTAT: SSP STATUS Register282Register 24-2: SSPCON1: SSP Control Register 1283Register 24-3: SSPCON2: SSP Control Register 2284Register 24-4: SSPCON3: SSP Control Register 3285Register 24-5: SSPMSK: SSP Mask Register286Register 24-6: SSPADD: MSSP Address and Baud Rate Register (I2C Mode)28625.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)287FIGURE 25-1: EUSART Transmit Block Diagram287FIGURE 25-2: EUSART Receive Block Diagram28825.1 EUSART Asynchronous Mode28925.1.1 EUSART Asynchronous Transmitter289FIGURE 25-3: Asynchronous Transmission290FIGURE 25-4: Asynchronous Transmission (Back-to-Back)290TABLE 25-1: Summary of Registers Associated with Asynchronous Transmission29125.1.2 EUSART Asynchronous Receiver292FIGURE 25-5: Asynchronous Reception294TABLE 25-2: Summary of Registers Associated with Asynchronous Reception29525.2 Clock Accuracy with Asynchronous Operation29625.3 Register Definitions: EUSART Control296Register 25-1: TXSTA: Transmit Status and Control Register296Register 25-2: RCSTA: Receive Status and Control Register(1)297Register 25-3: BAUDCON: Baud Rate Control Register29825.4 EUSART Baud Rate Generator (BRG)299EXAMPLE 25-1: Calculating Baud Rate Error299TABLE 25-3: Baud Rate Formulas300TABLE 25-4: Summary of Registers Associated with the Baud Rate Generator300TABLE 25-5: BAUD Rates for Asynchronous Modes30125.4.1 Auto-Baud Detect304TABLE 25-6: BRG Counter Clock Rates304FIGURE 25-6: Automatic Baud Rate Calibration30425.4.2 Auto-baud Overflow30525.4.3 Auto-Wake-up on Break305FIGURE 25-7: Auto-Wake-up bit (WUE) Timing during Normal Operation306FIGURE 25-8: Auto-Wake-up bit (WUE) Timings during Sleep30625.4.4 BREAK Character Sequence30725.4.5 Receiving a BREAK Character307FIGURE 25-9: Send Break Character Sequence30725.5 EUSART Synchronous Mode30825.5.1 Synchronous Master Mode308FIGURE 25-10: Synchronous Transmission309FIGURE 25-11: Synchronous Transmission (Through TXEN)309TABLE 25-7: Summary of Registers Associated with Synchronous Master Transmission309FIGURE 25-12: Synchronous Reception (Master Mode, SREN)311TABLE 25-8: Summary of Registers Associated with Synchronous Master Reception31125.5.2 Synchronous Slave Mode312TABLE 25-9: Summary of Registers Associated with Synchronous Slave Transmission312TABLE 25-10: Summary of Registers Associated with Synchronous Slave Reception31325.6 EUSART Operation During Sleep31425.6.1 Synchronous Receive During Sleep31425.6.2 Synchronous Transmit During Sleep31426.0 Capacitive Sensing (CPS) Module315FIGURE 26-1: Capacitive Sensing Block Diagram315FIGURE 26-2: Capacitive Sensing Oscillator Block Diagram31626.1 Analog MUX31726.2 Capacitive Sensing Oscillator31726.3 Voltage Reference Modes31726.4 Current Ranges318TABLE 26-1: Current Range Selection31826.5 Timer Resources31926.6 Fixed Time Base31926.6.1 Timer031926.6.2 Timer1319TABLE 26-2: TIMER1 ENABLE FUNCTION31926.7 Software Control31926.7.1 Nominal Frequency (No Capacitive Load)31926.7.2 Reduced Frequency (Additional Capacitive Load)31926.7.3 Frequency Threshold32026.8 Operation during Sleep32026.9 Register Definitions: CPS Control321Register 26-1: CPSCON0: Capacitive Sensing Control Register 0321Register 26-2: CPSCON1: Capacitive Sensing Control Register 1322TABLE 26-3: Summary of Registers Associated with Capacitive Sensing32327.0 Liquid Crystal Display (LCD) Driver Module325FIGURE 27-1: LCD Driver Module Block Diagram32527.1 LCD Registers326TABLE 27-1: LCD Segment and Data Registers32627.2 Register Definitions: LCD Control327Register 27-1: LCDCON: Liquid Crystal Display (LCD) Control Register327Register 27-2: LCDPS: LCD Phase Register328Register 27-3: LCDREF: LCD Reference Voltage Control Register329Register 27-4: LCDCST: LCD Contrast Control Register330Register 27-5: LCDSEn: LCD Segment Enable Registers331Register 27-6: LCDDATAn: LCD Data Registers33127.3 LCD Clock Source Selection33227.3.1 LCD Prescaler332FIGURE 27-2: LCD Clock Generation33227.4 LCD Bias Voltage Generation333TABLE 27-2: LCD Bias Voltages333FIGURE 27-3: LCD Bias Voltage Generation Block Diagram33327.5 LCD Bias Internal Reference Ladder33427.5.1 Bias Mode Interaction334TABLE 27-3: LCD Internal Ladder Power Modes (1/3 Bias)33427.5.2 Power Modes33427.5.3 Automatic Power Mode Switching335FIGURE 27-4: LCD Internal Reference Ladder Power Mode Switching Diagram – Type A335FIGURE 27-5: LCD Internal Reference Ladder Power Mode Switching Diagram – Type A Waveform (1/2 MUX, 1/2 Bias Drive)336FIGURE 27-6: LCD Internal Reference Ladder Power Mode Switching Diagram – Type B Waveform (1/2 MUX, 1/2 Bias Drive)337Register 27-7: LCDRL: LCD Reference Ladder Control Registers33827.5.4 Contrast Control339FIGURE 27-7: Internal reference and Contrast Control Block Diagram33927.5.5 Internal Reference33927.5.6 VLCD<3:1> Pins33927.6 LCD Multiplex Types340TABLE 27-4: Common Pin Usage34027.7 Segment Enables34027.8 Pixel Control34027.9 LCD Frame Frequency340TABLE 27-5: Frame Frequency Formulas340TABLE 27-6: Approximate Frame Frequency (in Hz) Using Fosc @ 8 MHz, Timer1 @ 32.768 kHz or LFINTOSC340TABLE 27-7: LCD Segment Mapping Worksheet34127.10 LCD Waveform Generation342FIGURE 27-8: Type-A/Type-B Waveforms in Static Drive342FIGURE 27-9: Type-A Waveforms in 1/2 MUX, 1/2 Bias Drive343FIGURE 27-10: Type-B Waveforms in 1/2 MUX, 1/2 Bias Drive344FIGURE 27-11: Type-A Waveforms in 1/2 MUX, 1/3 Bias Drive345FIGURE 27-12: Type-B Waveforms in 1/2 MUX, 1/3 Bias Drive346FIGURE 27-13: Type-A Waveforms in 1/3 MUX, 1/2 Bias Drive347FIGURE 27-14: Type-B Waveforms in 1/3 MUX, 1/2 Bias Drive348FIGURE 27-15: Type-A Waveforms in 1/3 MUX, 1/3 Bias Drive349FIGURE 27-16: Type-B Waveforms in 1/3 MUX, 1/3 Bias Drive350FIGURE 27-17: Type-A Waveforms in 1/4 MUX, 1/3 Bias Drive351FIGURE 27-18: Type-B Waveforms in 1/4 MUX, 1/3 Bias Drive35227.11 LCD Interrupts35327.11.1 LCD Interrupt on Module Shutdown35327.11.2 LCD Frame Interrupts353FIGURE 27-19: Waveforms and Interrupt Timing in Quarter-Duty Cycle Drive (Example – Type-B, Non-Static)35427.12 Operation During Sleep355TABLE 27-8: LCD Module Status During Sleep355FIGURE 27-20: Sleep Entry/Exit when SLPEN = 135627.13 Configuring the LCD Module35727.14 Disabling the LCD Module35727.15 LCD Current Consumption35727.15.1 Oscillator Selection35727.15.2 LCD Bias Source35727.15.3 Capacitance of the LCD Segments357TABLE 27-9: Summary of Registers Associated with LCD Operation35828.0 In-Circuit Serial Programming™ (ICSP™)35928.1 High-Voltage Programming Entry Mode359FIGURE 28-1: Vpp Limiter Example Circuit35928.2 Low-Voltage Programming Entry Mode36028.3 Common Programming Interfaces360FIGURE 28-2: ICD RJ-11 Style Connector Interface360FIGURE 28-3: PICkit™ Style Connector Interface360FIGURE 28-4: Typical Connection for ICSP™ Programming36129.0 Instruction Set Summary36329.1 Read-Modify-Write Operations363TABLE 29-1: Opcode Field Descriptions363TABLE 29-2: Abbreviation Descriptions363FIGURE 29-1: General Format for Instructions364TABLE 29-3: PIC16(L)F193X Enhanced Instruction Set365TABLE 29-3: PIC16(L)F193X Enhanced Instruction Set (Continued)36629.2 Instruction Descriptions36730.0 Electrical Specifications377Absolute Maximum Ratings(†)377FIGURE 30-1: PIC16F1938/9 Voltage Frequency Graph, -40°C £ Ta £ +125°C378FIGURE 30-2: PIC16LF1938/9 Voltage Frequency Graph, -40°C £ Ta £ +125°C378FIGURE 30-3: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature37930.1 DC Characteristics: PIC16(L)F1938/39-I/E (Industrial, Extended)380FIGURE 30-4: POR and POR Rearm with Slow Rising Vdd38130.2 DC Characteristics: PIC16F/LF1938/39-I/E (Industrial, Extended)38230.3 DC Characteristics: PIC16(L)F1938/39-I/E (Power-Down)38530.4 DC Characteristics: PIC16(L)F1938/39-I/E38730.5 Memory Programming Requirements38930.6 Thermal Considerations39030.7 Timing Parameter Symbology391FIGURE 30-5: Load Conditions39130.8 AC Characteristics: PIC16(L)F1938/39-I/E392FIGURE 30-6: Clock Timing392TABLE 30-1: Clock Oscillator Timing Requirements392TABLE 30-2: Oscillator Parameters393TABLE 30-3: PLL Clock Timing Specifications (Vdd = 2.7V to 5.5V)393FIGURE 30-7: CLKOUT and I/O Timing393TABLE 30-4: CLKOUT and I/O Timing Parameters394FIGURE 30-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing394FIGURE 30-9: Brown-Out Reset Timing and Characteristics395TABLE 30-5: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset396FIGURE 30-10: Timer0 and Timer1 External Clock Timings396TABLE 30-6: Timer0 and Timer1 External Clock Requirements397FIGURE 30-11: Capture/Compare/PWM Timings (CCP)397TABLE 30-7: Capture/Compare/PWM Requirements (CCP)397TABLE 30-8: PIC16(L)F1938/39 A/D Converter (ADC) Characteristics:(1),(2),(3)398TABLE 30-9: PIC16(L)F1938/39 A/D Conversion Requirements398FIGURE 30-12: PIC16(L)F1938/39 A/D Conversion Timing (Normal Mode)399FIGURE 30-13: PIC16(L)F1938/39 A/D Conversion Timing (Sleep Mode)399TABLE 30-10: Comparator Specifications400TABLE 30-11: Digital-to-Analog Converter (DAC) Specifications400FIGURE 30-14: USART Synchronous Transmission (Master/Slave) Timing400TABLE 30-12: USART Synchronous Transmission Requirements401FIGURE 30-15: USART Synchronous Receive (Master/Slave) Timing401TABLE 30-13: USART Synchronous Receive Requirements401FIGURE 30-16: SPI Master Mode Timing (CKE = 0, SMP = 0)402FIGURE 30-17: SPI Master Mode Timing (CKE = 1, SMP = 1)402FIGURE 30-18: SPI Slave Mode Timing (CKE = 0)403FIGURE 30-19: SPI Slave Mode Timing (CKE = 1)403TABLE 30-14: SPI Mode Requirements404FIGURE 30-20: I2C™ Bus Start/Stop Bits Timing404TABLE 30-15: I2C™ Bus Start/Stop Bits Requirements405FIGURE 30-21: I2C™ Bus Data Timing405TABLE 30-16: I2C™ Bus Data Requirements406TABLE 30-17: Cap Sense Oscillator Specifications407FIGURE 30-22: Cap Sense Oscillator40731.0 DC and AC Characteristics Graphs and Charts409FIGURE 31-1: Idd, LP Oscillator, Fosc = 32 kHz, PIC16LF1938/9 Only410FIGURE 31-2: Idd, LP Oscillator, Fosc = 32 kHz, PIC16F1938/9 Only410FIGURE 31-3: Idd Typical, XT and EXTRC Oscillator, PIC16LF1938/9 Only411FIGURE 31-4: Idd Maximum, XT and EXTRC Oscillator, PIC16LF1938/9 Only411FIGURE 31-5: Idd Typical, XT and EXTRC Oscillator, PIC16F1938/9 Only412FIGURE 31-6: Idd Maximum, XT and EXTRC Oscillator, PIC16F1938/9 Only412FIGURE 31-7: Idd, External Clock (ECL), Low-Power Mode, Fosc = 32 kHz, PIC16LF1938/9 Only413FIGURE 31-8: Idd, External Clock (ECL), Low-Power Mode, Fosc = 32 kHz, PIC16F1938/9 Only413FIGURE 31-9: Idd, External Clock (ECL), Low-Power Mode, Fosc = 500 kHz, PIC16LF1938/9 Only414FIGURE 31-10: Idd, External Clock (ECL), Low-Power Mode, Fosc = 500 kHz, PIC16F1938/9 Only414FIGURE 31-11: Idd Typical, External Clock (ECM), Medium-Power Mode, PIC16LF1938/9 Only415FIGURE 31-12: Idd Maximum, External Clock (ECM), Medium-Power Mode, PIC16LF1938/9 Only415FIGURE 31-13: Idd Typical, External Clock (ECM), Medium-Power Mode, PIC16F1938/9 Only416FIGURE 31-14: Idd Maximum, External Clock (ECM), Medium-Power Mode, PIC16F1938/9 Only416FIGURE 31-15: Idd Typical, External Clock (ECH), High-Power Mode, PIC16LF1938/9 Only417FIGURE 31-16: Idd Maximum, External Clock (ECH), High-Power Mode, PIC16LF1938/9 Only417FIGURE 31-17: Idd Typical, External Clock (ECH), High-Power Mode, PIC16F1938/9 Only418FIGURE 31-18: Idd Maximum, External Clock (ECH), High-Power Mode, PIC16F1938/9 Only418FIGURE 31-19: Idd, LFINTOSC, Fosc = 31 kHz, PIC16LF1938/9 Only419FIGURE 31-20: Idd, LFINTOSC, Fosc = 31 kHz, PIC16F1938/9 Only419FIGURE 31-21: Idd, MFINTOSC, Fosc = 500 kHz, PIC16LF1938/9 Only420FIGURE 31-22: Idd, MFINTOSC, Fosc = 500 kHz, PIC16F1938/9 Only420FIGURE 31-23: Idd Typical, HFINTOSC, PIC16LF1938/9 Only421FIGURE 31-24: Idd Maximum, HFINTOSC, PIC16LF1938/9 Only421FIGURE 31-25: Idd Typical, HFINTOSC, PIC16F1938/9 Only422FIGURE 31-26: Idd Maximum, HFINTOSC, PIC16F1938/9 Only422FIGURE 31-27: Idd Typical, HS Oscillator, PIC16LF1938/9 Only423FIGURE 31-28: Idd Maximum, HS Oscillator, PIC16LF1938/9 Only423FIGURE 31-29: Idd Typical, HS Oscillator, PIC16F1938/9 Only424FIGURE 31-30: Idd Maximum, HS Oscillator, PIC16F1938/9 Only424FIGURE 31-31: Ipd Base, Low-Power Sleep Mode, PIC16LF1938/9 Only425FIGURE 31-32: Ipd Base, Low-Power Sleep Mode, PIC16F1938/9 Only425FIGURE 31-33: Ipd, Watchdog Timer (WDT), PIC16LF1938/9 Only426FIGURE 31-34: Ipd, Watchdog Timer (WDT), PIC16F1938/9 Only426FIGURE 31-35: Ipd, Fixed Voltage Reference (FVR), PIC16LF1938/9 Only427FIGURE 31-36: Ipd, Fixed Voltage Reference (FVR), PIC16F1938/9 Only427FIGURE 31-37: Ipd, Brown-Out Reset (BOR), BORV = 0, PIC16LF1938/9 Only428FIGURE 31-38: Ipd, Brown-Out Reset (BOR), BORV = 0, PIC16F1938/9 Only428FIGURE 31-39: Ipd, Timer1 Oscillator, Fosc = 32 kHz, PIC16LF1938/9 Only429FIGURE 31-40: Ipd, Timer1 Oscillator, Fosc = 32 kHz, PIC16F1938/9 Only429FIGURE 31-41: Ipd, Capacitive Sensing (CPS) Module, Low-Current Range (CPSRM = 0, CPSRNG = 01), PIC16LF1938/9 Only430FIGURE 31-42: Ipd, Capacitive Sensing (CPS) Module, Low-Current Range (CPSRM = 0, CPSRNG = 01), PIC16F1938/9 Only430FIGURE 31-43: Ipd, Capacitive Sensing (CPS) Module, Medium-Current Range (CPSRM = 0, CPSRNG = 10), PIC16LF1938/9 Only431FIGURE 31-44: Ipd, Capacitive Sensing (CPS) Module, Medium-Current Range (CPSRM = 0, CPSRNG = 10), PIC16F1938/9 Only431FIGURE 31-45: Ipd, Capacitive Sensing (CPS) Module, High-Current Range (CPSRM = 0, CPSRNG = 11), PIC16LF1938/9 Only432FIGURE 31-46: Ipd, Capacitive Sensing (CPS) Module, High-Current Range (CPSRM = 0, CPSRNG = 11), PIC16F1938/9 Only432FIGURE 31-47: Ipd, Comparator, Low-Power Mode, (CxSP = 0), PIC16LF1938/9 Only433FIGURE 31-48: Ipd, Comparator, Low-Power Mode, (CxSP = 0), PIC16F1938/9 Only433FIGURE 31-49: Ipd, Comparator, Normal-Power Mode, (CxSP = 1), PIC16LF1938/9 Only434FIGURE 31-50: Ipd, Comparator, Normal-Power Mode, (CxSP = 1), PIC16F1938/9 Only434FIGURE 31-51: Voh vs. Ioh Over Temperature, Vdd = 5.0V, PIC16F1938/9 Only435FIGURE 31-52: Vol vs. Iol Over Temperature, Vdd = 5.0V, PIC16F1938/9 Only435FIGURE 31-53: Voh vs. Ioh Over Temperature, Vdd = 3.0V436FIGURE 31-54: Vol vs. Iol Over Temperature, Vdd = 3.0V436FIGURE 31-55: Voh vs. Ioh Over Temperature, Vdd = 1.8V437FIGURE 31-56: Vol vs. Iol Over Temperature, Vdd = 1.8V437FIGURE 31-57: POR Release Voltage438FIGURE 31-58: POR Rearm Voltage, PIC16F1938/9 Only438FIGURE 31-59: Brown-out Reset Voltage, BORV = 1439FIGURE 31-60: Brown-out Reset Hysteresis, BORV = 1439FIGURE 31-61: Brown-out Reset Voltage, BORV = 0440FIGURE 31-62: Brown-out Reset Hysteresis, BORV = 0440FIGURE 31-63: WDT Time-out Period441FIGURE 31-64: PWRT Period441FIGURE 31-65: Comparator Hysteresis, Normal-Power Mode (CxSP = 1, CxHYS = 1)442FIGURE 31-66: Comparator Hysteresis, Low-Power Mode (CxSP = 0, CxHYS = 1)442FIGURE 31-67: Comparator Response Time, Normal-Power Mode, (CxSP = 1)443FIGURE 31-68: Comparator Response Time Over Temperature, Normal-Power Mode (CxSP = 1)443FIGURE 31-69: Comparator Input Offset at 25°C, Normal-Power Mode, (CxSP = 1), PIC16F1938/9 Only44432.0 Development Support44532.1 MPLAB X Integrated Development Environment Software44532.2 MPLAB XC Compilers44632.3 MPASM Assembler44632.4 MPLINK Object Linker/ MPLIB Object Librarian44632.5 MPLAB Assembler, Linker and Librarian for Various Device Families44632.6 MPLAB X SIM Software Simulator44732.7 MPLAB REAL ICE In-Circuit Emulator System44732.8 MPLAB ICD 3 In-Circuit Debugger System44732.9 PICkit 3 In-Circuit Debugger/ Programmer44732.10 MPLAB PM3 Device Programmer44732.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits44832.12 Third-Party Development Tools44833.0 Packaging Information44933.1 Package Marking Information449Package Marking Information (Continued)450Package Marking Information (Continued)451Package Marking Information (Continued)45233.2 Package Details453Appendix A: Data Sheet Revision History473Revision A (05/2011)473Revision B (02/2012)473Revision C (06/2013)473Appendix B: Migrating From Other PIC® Devices473TABLE B-1: Feature Comparison473INDEX475A475B475C475D476E476F477I477L477M478O478P478R479S479T480U481V481W481The Microchip Web Site483Customer Change Notification Service483Customer Support483Product Identification System485Trademarks487Worldwide Sales488Tamanho: 9 MBPáginas: 488Language: EnglishAbrir o manual
