Microchip Technology MA330018 Ficha De Dados
© 2007-2012 Microchip Technology Inc.
DS70291G-page 41
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
4.2.5
X AND Y DATA SPACES
The core has two data spaces, X and Y. These data
spaces can be considered either separate (for some
DSP instructions), or as one unified linear address
range (for MCU instructions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms
such as Finite Impulse Response (FIR) filtering and
Fast Fourier Transform (FFT).
The X data space is used by all instructions and
supports all addressing modes. X data space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
data space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MAC class).
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths.
Both the X and Y data spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for writes to X data space.
All data memory writes, including in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent and is not user-programmable.
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes, or 32K words, though the
implemented memory locations vary by device.
spaces can be considered either separate (for some
DSP instructions), or as one unified linear address
range (for MCU instructions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms
such as Finite Impulse Response (FIR) filtering and
Fast Fourier Transform (FFT).
The X data space is used by all instructions and
supports all addressing modes. X data space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
data space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MAC class).
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths.
Both the X and Y data spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for writes to X data space.
All data memory writes, including in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent and is not user-programmable.
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes, or 32K words, though the
implemented memory locations vary by device.
4.2.6
DMA RAM
Every dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 device contains
up to 2 Kbytes of dual ported DMA RAM located at
the end of Y data space, and is a part of Y data
space. Memory locations in the DMA RAM space are
accessible simultaneously by the CPU and the DMA
controller module. The DMA RAM is utilized by the
DMA controller to store data to be transferred to
various peripherals using DMA, as well as data
transferred from various peripherals using DMA. The
DMA RAM can be accessed by the DMA controller
without having to steal cycles from the CPU.
When the CPU and the DMA controller attempt to
concurrently write to the same DMA RAM location, the
hardware ensures that the CPU is given precedence in
accessing the DMA RAM location. Therefore, the DMA
RAM provides a reliable means of transferring DMA
data without ever having to stall the CPU.
X04 and dsPIC33FJ128MCX02/X04 device contains
up to 2 Kbytes of dual ported DMA RAM located at
the end of Y data space, and is a part of Y data
space. Memory locations in the DMA RAM space are
accessible simultaneously by the CPU and the DMA
controller module. The DMA RAM is utilized by the
DMA controller to store data to be transferred to
various peripherals using DMA, as well as data
transferred from various peripherals using DMA. The
DMA RAM can be accessed by the DMA controller
without having to steal cycles from the CPU.
When the CPU and the DMA controller attempt to
concurrently write to the same DMA RAM location, the
hardware ensures that the CPU is given precedence in
accessing the DMA RAM location. Therefore, the DMA
RAM provides a reliable means of transferring DMA
data without ever having to stall the CPU.
4.3
Memory Resources
Many useful resources related to Memory Organization
are provided on the main product page of the Microchip
web site for the devices listed in this data sheet. This
product page, which can be accessed using this
are provided on the main product page of the Microchip
web site for the devices listed in this data sheet. This
product page, which can be accessed using this
contains the latest updates and additional information.
4.3.1
KEY RESOURCES
• Section 4. “Program Memory” (DS70203)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related dsPIC33F/PIC24H Family Reference
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related dsPIC33F/PIC24H Family Reference
Manuals Sections
• Development Tools
Note:
The DMA RAM can be used for general
purpose data storage if the DMA function
is not required in an application.
purpose data storage if the DMA function
is not required in an application.
Note:
In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
product page using the link above, enter
this URL in your browser: